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Boundary-Scan Blog |
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01/30/12
Remote Diagnostics Display - ScanExpress Runner
Introduction
Corelis ScanExpress Runner software includes a hidden remote diagnostic display feature that allows the user to view the results of a previous test failure. This feature is most useful when you need to view test diagnostics but either do not have the hardware available or do not want to rerun the test. In fact, our tech support and applications engineers use this feature all the time to assist with problems around the globe.
Required Files
ScanExpress Runner generates a result file for each test step that fails. The result file, along with the original test step, allows ScanExpress Runner to recreate the test results and diagnostics.
There are two types of result files—one for infrastructure type tests, and one for interconnect type tests.
The required infrastructure test files are:
- CVF file – This file contains the infrastructure test vectors. This file is generated by ScanExpress TPG using the Infrastructure button selection and the file name has the ‘_inf.cvf’ suffix.
- CRF File - This file contains the results of the infrastructure test and the file name has the ‘_inf.crf’ suffix. This file is created only in the case of an infrastructure test failure. If the infrastructure test passes, this file is not created and attempting to remote diagnosing the test always results in a Run Error (further explained later in the document).
In order to simulate interconnect type test steps (interconnect, buswire, memory, pull/pull-down, & cluster), the following two files are required:
- CVF file – This file contains the test vectors that were generated by ScanExpress TPG. The file name must have one of the following suffixes: ‘_int.cvf’, ‘_bus.cvf’, ‘_mct.cvf’, ‘_pull.cvf’, ‘_ct.cvf’
- RES file – This file contains the results of the test step. Suffixes: ‘_int.res’, ‘_bus.res’, ‘_mct.res’, ‘_pull.cvf’, ‘_ct.res’.
Viewing Remote Diagnostics
Viewing remote diagnostics is just like running a test. Once invoked, ScanExpress Runner will go through the internal run process and use the existing results instead of the JTAG controller.
To run the test in remote diagnostics mode, simply depress the and keys simultaneously and click the key once. You will see the prompt below.
In order to proceed, dismiss the message box by selecting Append or Overwrite. Pressing Cancel terminates the simulation.
The test plan will execute in the same way it would on hardware. Runner will display the test results (including ADO if licensed) in the test results windows.
Note: Passing test steps will not generate the required remote diagnostics files. These test steps may show a “Run Error” when executed in remote diagnostics mode.
Conclusion
Remote diagnostics are a handy way to examine, troubleshoot, and diagnose test failures without the UUT. There’s no need to tie up a lab or production station—simply transfer the files over to your office station with Runner and perform in-depth failure analysis at your leisure.
Blind and Buried Vias
We often talk about system, circuit, and PCB complexities driving the transition toward boundary-scan, but what do these refer to? We often list the hurdles: BGAs, blind & buried vias, stacked dies, complex components on both sides of the PCB, smaller and denser PCBs—the list goes on. Let’s take a quick look at one set of item on this list: blind & buried vias. While not new technologies, these techniques are part of a greater trend of squeezing more capability into a smaller space.
Definitions
Controlled drilling techniques have opened up the possibility for denser multi-layer circuit boards. By shortening vias to only pass through necessary layers, more surface area on both sides can be opened up for components.
Figure 1: Diagram of a Printed Circuit Board
Blind Via
A blind via extends to only one surface of the printed circuit board. Blind vias may be used for SMT or BGA pads. Because blind vias touch the surface on one side of the board they may be accessible to physical probes.
Buried Via
A buried via does not extend to either surface of the printed circuit board. Buried vias are not directly accessible to external probes.
What does it mean for circuit test?
A via that is not accessible from the surface of the board is, by extension, not available to external probes from test machines. Sure, you could bring out a test point for the net, but there’s a good chance that the point of using a buried or blind via in the first place—to help reduce the amount of surface needed on the PCB!
Boundary-scan & JET have the advantage over ICT in these respects: instead of bringing all critical nets to the top of the board, you can bring the test straight to the net and have the same digital net & pin level diagnostics you would get for surface faults.
Conclusion
Boundary-scan is a great way to increase test coverage even when already using an ICT or as a lower cost alternative for designs with a low probe access. For those integrating into an ICT, check out our ICT integration web pages In-Circuit Tester Integration & Support for In-Circuit Testers and Flying Probes.
01/12/12
Package-on-Package (PoP) handling with ScanExpress Boundary-scan Tools
Package-on-package (PoP), a method to stack discrete packages vertically, has over the last few years gained significant popularity with applications processors such as Texas Instruments OMAP and DaVinci DM37x series SOCs. As with many space-saving design techniques, implementing PoP can often result in loss of physical test access since connections between the bottom and top devices are inaccessible to probes, making boundary-scan ideal for testing the interfaces.
To make matters worse, not all design engineers define a PoP interface the same way—some may choose to define each net in the schematic/netlist, while others may consider interconnections to be implied and outside the scope of the PCB design files. Many designers will define the PoP connections outside of the PCB files, leaving automated tools without an interface definition.
Let’s take a look at a few cases and how to set up ScanExpress tools for projects that include PoP components based on different possibilities.
Figure 1: Processors with PoP interfaces include interconnections on the top and bottom
Before You Start: Check for Boundary-scan Access!
Not all CPUs include boundary-scan cells on the PoP interface. For example, the TI DM3725 CBP and CBC packages offer no boundary-scan access on the top RAM interface. It’s always a good idea to check the BSDL first and make sure that boundary-scan is supported on a particular set of pins before going deep into test development.
To verify boundary-scan capability, open up the BSDL and search for a few PoP pins. Make sure that the pin in the BSDL file is associated with a digital port and that the port is associated with cells in the boundary-scan register (BSR). If the component is a synchronous memory device, start with the clock—clock pins are the most likely pin to be left out of the BSR due to high speed requirements and on-chip PLLs that limit boundary-scan capability.
Handling Common Cases
Keep in mind that not all design files will define the PoP interface in the same way. Some designers may choose to leave any reference to the PoP interface out of the system schematic and netlist—this makes complete sense considering the way PCBs have traditionally been defined and built, but unfortunately makes test definition more difficult for the test engineer.
Case 1: PoP Defined in the Netlist
If the PoP interface is fully described in the system netlist, then you’re in luck—the tedious work was already done! Setting up the test should be a simple process to associate a BSDL file with the CPU and associate an appropriate model with the PoP device. ScanExpress TPG will treat the top balls on the PoP just like other board interconnects and generate tests accordingly to catch opens, shorts, and bridging faults wherever possible.
Case 2: PoP Not Defined
In some cases, the PoP interconnect and device definitions will be left out of the netlist entirely and the test engineer not be provided an external netlist or connection list. In these situations, there are two main approaches with ScanExpress Tools:
Edit the original netlist directly to add the PoP-to-peripheral connections, then use the edited netlist to create a ScanExpress project.
Use ScanExpress netlist edit commands to define the connections between the CPU and peripheral. This may include a mix of ADD_NODE, ADD_NET, and sometimes MERGE_NET commands.
For example, let’s say that applications processor U1 has a PoP interface populated by device U10, as shown below. The schematic and Netlist have no reference to U10 or the PoP pins on U1.
Figure 2: PoP & PCB Interface Interconnections
Using approach #1, we can edit the source netlist to add the additional net definitions. Editing the netlist directly has the advantage of making the nets available to the TPG preparation flow immediately and allowing these nets to be used in the scripting engine. The disadvantage is that it requires modifying the source netlist, which may or may not be an acceptable method.
A good text editor with block edit capabilities such as TextPad can make editing the netlist easy. Since the interface is one-to-one, each pin can be copied and pasted to form the net. For example, the new nets might look something like this:
Code:
$NETS
‘POP_NET_T1’ ; U1.T1 U10.T1
‘POP_NET_T2’ ; U1.T2 U10.T2
‘POP_NET_T3’ ; U1.T3 U10.T3
Note: If a netlist detailing the PoP interface is available, ScanExpress Merge may be used to combine the two netlists. Make sure that the reference designator for the boundary-scan device is the same in both netlists and turn of the “Add Prefix” option.Using approach #2, we will be adding netlist edit commands within TPG. This leaves the netlist file itself untouched, but takes a bit more definition and does not make the new nets available to the scripting engine. Keep in mind also that netlist edit commands are processed by the TPG generation engine and not the preparation engine, meaning any model associations will need to be done manually by editing input files. For example, we could add something like the following to the EDT file:
Code:
ADD_NET POP_NET_T1
ADD_NET POP_NET_T2
ADD_NET POP_NET_T3
ADD_NODE U1.T1 U10.T1 POP_NET_T1
ADD_NODE U1.T2 U10.T2 POP_NET_T2
ADD_NODE U1.T3 U10.T3 POP_NET_T3
ConclusionBeyond PoP, we expect to see more 2.5D and 3D techniques come into play in the next few years. If you have a design that uses PoP, 2.5D, 3D, or any difficult packaging method either at the board or chip level, let us know! Insight into your latest design developments helps us make sure ScanExpress tools remain easy to use for all possible UUT designs.
12/08/11
Boundary-scan System with Expert Test Services
Read on to learn how TestGenie helps growing companies incrementally add boundary-scan test capabilities using Corelis' TestGenie bundled hardware, software, and test service system.
Corelis TestGenie Is Ideal for Growing Organizations
Growing organizations face significant challenges—not the least of which is expanding production capacity while keeping overhead costs low. Take for example a medium sized vendor of electronic equipment facing increased demand for their product. Increased demand means ramping up production and increased production requires more thorough and efficient processes, especially for an organization focused on providing reliable, high quality products. How can an organization improve test processes and meet test coverage requirements incrementally, with minimal upfront investment?
In-Circuit Test (ICT) is likely out of the question—the fixture costs alone would break the budget, not to mention the high cost of owning or leasing time on the machine. Flying probe systems can save cost by forgoing the fixture requirement, but probe access on modern products is limited. System printed circuit boards (PCBs) continue to get smaller and denser, resulting in modern systems packed with ball grid array (BGA) parts and no room for test points. Traditional, intrusive test methodologies are unable to test interconnects on these products, leaving boundary-scan—a non-intrusive board test method—as the main option.
TestGenie is designed to minimize risk for companies
looking to integrate boundary-scan testing into their process.
Even JTAG/boundary-scan tools—already a low cost alternative to ICT—can be a significant investment in both products and engineering resources. While a large company can justify dedicating staff to test development and maintenance with their product volumes, many smaller organizations cannot afford such luxury. For this reason Corelis offers TestGenie—a low-cost, turnkey test solution for organizations with time-to-market pressures, tight budgets, and limited engineering resources. TestGenie is a complete boundary-scan test system tailored to a particular electronic system design and packaged to be easy and convenient for any size company. By allowing the test experts at Corelis to take care of boundary-scan test development, organizations can keep their valuable engineers working on core product features while still maintaining high quality standards and fast production.
The Corelis TestGenie system was designed to be easily integrated into any test process. For example, a basic fixtureless test process may first test newly assembled electronic products for power-on faults, and then proceed to TestGenie boundary-scan tests for structural fault detection and diagnosis. The boundary-scan tests—depending on system complexity—will usually execute in a matter of seconds and can be followed by in-system programming within the same test procedure and without requiring an additional station. TestGenie also includes Corelis’ advanced diagnostics and viewer modules for quick identification and visualization of fault causes to expedite repairs.
TestGenie includes ScanExpress software modules for execution, fault diagnosis, and fault visualization.
Choosing the wrong test solution can result in product delays and costly engineering effort. TestGenie facilitates boundary-scan test with minimal effort and helps mid-size organizations to meet increasing product demand while minimizing the impact on schedule and resources. Corelis TestGenie brings high quality test capabilities with a wide variety of needs. As demand grows, TestGenie can grow too—additional test stations for the same product design are available at discounted rates to keep up with increased production without requiring a major investment.
www.corelis.com/TestGenie
11/18/11
AMD CPU Support
JET support for AMD Turion™ II Neo, Athlon™ II Neo, Opteron™ 4100, and Opteron™ Quad-Core (socket F) CPUs is now available. This is the first product of its kind for AMD CPUs--enabling quick CPU driven functional test using the JTAG port of supported CPUs.
The AMD CPU support package includes auto-generated tests for the CPU and common peripherals, featuring:
- CPU Initialization
- Northbridge & Southbridge Initialization
- Hypertransport
- PCI/PCIe
- SPI Flash
- I2C Discovery
- UART Loopback
- Ethernet Loopback
Also included in the package is a Sage SmartProbe JTAG controller. The SmartProbe comes with adapters for popular AMD JTAG interfaces, including HDT, HDT+, and EDI.
Note that AMD system architecture is slightly more complex than the usual embedded CPU support for JET--we have a Northbridge and Southbridge in the equation. ScanExpress JET generates initialization scripts and tests for both support chips, enabling testing through peripheral interfaces outside of the CPU such as the PCIe interface of the Northbridge and SPI Flash interface of the Southbridge. Hypertransport tests verify operation of the high speed HT3 interface between the CPU and Northbridge at-speed without requiring any external probes.
A data sheet may be downloaded from our website using the link below (data sheet registration required).
Download the AMD CPU Support Datasheet
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