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Boundary-Scan Chain
Successful testing and ISP of your design depends on a fully
functional boundary-scan chain. Maximum test coverage is
achieved by testing all JTAG devices simultaneously.
Outline
Scan-Chain
Scan Chain Debug Access & Test Points


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Check devices for full JTAG compliance
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Some devices support emulation only or ISP only and
cannot be utilized for interconnect tests. Check
datasheets, device errata and BSDL files.
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Place devices in BYPASS that do not include a
boundary-scan register or do not support the EXTEST
instruction
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Group components with similar voltage levels
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Treat TCK as a critical high speed clock signal during
layout
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Always consider signal loading on the common signals TCK
and TMS and proper routing for good signal quality
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Dedicate a schematic page for a block diagram of the
JTAG scan-chain

JTAG Interface
Connector (TAP)
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Recommend Corelis JTAG TAP pin-out for robust one-to-one
connection between the JTAG controller and the target
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A solid ground is very important
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JTAG signal termination
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Multiple JTAG TAP connectors

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Connector
types
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Although different pinouts, most vendors use standard
0.1” x 0.1” pitch headers
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Shrouded header recommended to prevent incorrect
insertion
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2mm
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0.050” x 0.050”
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Test points for fixture probe access
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Edge connectors
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Backplane
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Keep
JTAG TAP cables as short as possible
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When using custom cable adapters, ensure adequate
grounding between the JTAG controller and the target
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3rd party JTAG tools may require a separate
JTAG TAP
connection for an individual component

Jumper example to isolate a single device

Logic example to isolate a single device
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Corelis Education

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Design engineers will benefit by
implementing a boundary-scan friendly design. |
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Corelis
offers free
three-day training classes that include a boundary-scan tutorial and
hands-on lab exercises using Corelis ScanExpress hardware and software.
The training class covers all aspects of boundary-scan testing using
Corelis ScanExpress tools. |
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