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Boundary-Scan Chain

Successful testing and ISP of your design depends on a fully functional boundary-scan chain.  Maximum test coverage is achieved by testing all JTAG devices simultaneously.

Outline


Scan-Chain

  • Place all JTAG devices into a single scan-chain and add test points for debug access.

    • All JTAG devices are tested simultaneously in the serial chain.

    Boundary-Scan Chain

     

  • Multiple scan-chains are acceptable but should be merged externally; in some cases this is the preferred method:

    • Use a multi-TAP JTAG controller to externally combine multiple JTAG scan-chains into a single chain. Each JTAG TAP is actively buffered and can interface to different voltage levels.

    • Alternatively combine multiple chains with a fixture or cable. Lower reliability and susceptible to noise.

    Multiple Scan-Chains

Scan Chain Debug Access & Test Points

Scan Chain Debug Access & Test Points

Scan Chain Debug Access & Test Points - Problematic components

  • Check devices for full JTAG compliance

    • Some devices support emulation only or ISP only and cannot be utilized for interconnect tests. Check datasheets, device errata and BSDL files.

    • Place devices in BYPASS that do not include a boundary-scan register or do not support the EXTEST instruction

  • Group components with similar voltage levels

    • Utilize a multi-JTAG TAP controller for programmable voltage interfacing or add level shifting components to the design

  • Treat TCK as a critical high speed clock signal during layout

  • Always consider signal loading on the common signals TCK and TMS and proper routing for good signal quality

    • Add TCK and TMS buffering on target when driving a large number of JTAG devices (more than 5)

  • Dedicate a schematic page for a block diagram of the JTAG scan-chain

Schematic page for a block diagram of the JTAG scan-chain

 


JTAG Interface Connector (TAP)

  • Corelis recommends the Corelis JTAG TAP pin-out for robust one-to-one connection between the JTAG controller and the target

    • Every other pin is ground on cable providing noise immunity

  • A solid ground is very important

  • JTAG signal termination

  • Multiple JTAG TAP connectors

    • Group by IC vendor

    • Group by voltage

    • Group by maximum device

    • Group by devices that requires

    • TMS, TCK, TRST_N signal

    • Chain isolation debug

    TAP Interface Connector

     

  • JTAG Interface Connector (TAP)Connector types

    • Although different pinouts, most vendors use standard
      0.1" x 0.1" pitch headers

    • Shrouded header recommended to prevent incorrect insertion

    • 2mm

    • 0.050" x 0.050"

    • Test points for fixture probe access

    • Edge connectors

    • Backplane

  • Keep JTAG TAP cables as short as possible

    • Ideally under 12" in length, shorter is better

  • When using custom cable adapters, ensure adequate grounding between the JTAG controller and the target

  • 3rd party JTAG tools may require a separate JTAG TAP connection for an individual component

Jumper example to isolate a single device

Jumper example to isolate a single device


Logic example to isolate a single device

Logic example to isolate a single device

 

 

     

 

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Corelis Education

 

     
 

Design engineers will benefit by implementing a boundary-scan friendly design.

 
 

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Corelis offers free three-day training classes that include a boundary-scan tutorial and hands-on lab exercises using Corelis ScanExpress hardware and software.  The training class covers all aspects of boundary-scan testing using Corelis ScanExpress tools.

 
 

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