San Jose, CA, April 14, 2008 – Corelis Inc., a leading supplier of high-performance JTAG development tools for embedded microprocessors, announced today that its CodeSymphony software development and JTAG debug environment has been enhanced to support the new AMCC PowerPC 460EX Canyonlands and 460GT Glacier platforms. CodeSymphony, an integrated development environment (IDE) based on Eclipse, is included in the AMCC Evaluation Kits for these and other AMCC platforms. In addition to the usual user-level access and debug features, CodeSymphony’s JTAG-based debugging adds board bring-up support and kernel-level debug capabilities. Corelis is demonstrating CodeSymphony for multi-core debug of the PowerPC 460EX at the Embedded Systems Conference exhibition (booth #2226), April 15-17, 2008, in San Jose, California.

The Eclipse IDE is exceptionally flexible because of its open, extensible plug-in based architecture. Eclipse is a platform that is rapidly emerging as a standard for the embedded systems industry. It provides developers with an advanced embedded tool suite that allows them to build, compile, and debug their embedded applications faster than ever before, thereby reducing their time to market for PowerPC 4xx-based systems. With this IDE, CodeSymphony provides for complete management of a developer’s project using a simple graphical user interface. Developers can set up one or more build environments by specifying the compiler and build options, allowing for quick and easy revisions of their projects. CodeSymphony includes a pre-built GNU C/C++ cross tool-chain for Linux and Windows. The tool-chain includes a compiler, linker and debugger, along with other tools configured for PowerPC targets.

Developers use CodeSymphony to step, run, halt, and perform other operations to examine and debug their code. By incorporating the use of Eclipse and GDB, both popular open source applications, the learning curve for developers is greatly diminished. The basic version of CodeSymphony provides register and memory control functions plus additional features and commands to complement GDB, such as the ability to read special purpose registers, set hardware breakpoints, and other target hardware specific features. When upgraded to the JTAG-based version of CodeSymphony, users have access to advanced features including support for board bring-up, partial functionality debug, boot loader debug, kernel-level debug, and optional flash memory programming.

“Our customers appreciate the fact that the Corelis CodeSymphony tools are included in many of our current evaluation kits,” said Charlie Ashton, Director of Enablement at AMCC. “We are pleased that these tools will be available in the new PowerPC 460EX and 460GT evaluation kits too. We know that many of our customers use CodeSymphony as well as the Corelis JTAG tools so we welcome the availability of these products supporting the new high end 460EX and 460GT processors."

"Once again, we are delighted to supply development tool technology for AMCC’s PowerPC platforms. CodeSymphony provides best-in-class support and flexibility for our users in the embedded market regardless of whether they prefer Windows or Linux," said Andrew Levy, Director of Marketing at Corelis. "Furthermore, through JTAG emulation, customers can readily migrate their application from AMCC’s evaluation board to their actual target board."

For the AMCC Evaluation Kits, CodeSymphony uses the on-board gdbserver and Ethernet interface to connect to the board. The user can upgrade CodeSymphony to JTAG emulation by purchasing a USB 2.0 or Ethernet JTAG controller. This is essential for bringing up new target hardware or when there is no on-board monitor or gdbserver. To meet the requirements of today’s most demanding applications, these controllers use a high-speed boundary-scan controller architecture based on Corelis’ proprietary "Turbo Scan Engine." Corelis also complements CodeSymphony emulators with ScanExpress™ JET (JTAG Emulation Test), a suite of on-board functional test tools that leverage the AMCC processors’ JTAG port to exercise the surrounding circuitry for at-speed functional testing.