Corelis family of SCANIO™ modules turn any IEEE-std-1149.1 boundary-scan controller into a powerful digital boundary-scan tester. The SCANIO™ family of products use boundary-scan gate arrays to add control and visibility to connectors, traces, and logic that is otherwise can not be tested using traditional boundary-scan techniques.

The SCANIO™ products, when combined with a boundary-scan controller, operate as a traditional "bed-of-nails" tester except access to the stimulus and response I/O's is achieved via boundary-scan.

A listing of available SCANIO™ modules is provided in the following table:

Product Selection Matrix

 

ScanIO-300LV The ScanIO-300LV digital I/O module turns an IEEE-1149.1 boundary-scan controller (such as the Corelis PCI-1149.1/Turbo™ or NetUSB-1149.1™) into a powerful digital interconnect and functional tester. It uses boundary-scan compatible ASICs to add control and visibility to connectors, traces, and logic that are otherwise untestable using traditional scan techniques. The ScanIO-300LV, combined with a boundary-scan controller, operates as a traditional “bed of nails” test system except access to the stimulus-and response I/Os is achieved via boundary-scan, and the size and the cost of the system are significantly smaller than traditional testers. The ScanIO-300LV module provides a total of 300 fully bidirectional test channels with virtually unlimited memory depth per pin. Each line is independently controlled and can be individually configured as an input or output. During testing, the programming and control of the test channels is automatically performed by the ScanPlus™/ScanExpress™ tools without any user intervention. The voltage level of the I/O and JTAG interfaces is programmable from 1.25V to 3.3V and supports either single ended or low voltage differential (LVDS) signaling. Multiple ScanIO-300LV modules can be cascaded in series providing a sufficient number of pins for almost any digital test environment. By using single or multiple ScanIO-300LV modules, existing Automatic Test Pattern Generators (ATPGs) can be used to test non-scannable elements such as connectors, cables, and devices not incorporating boundary-scan. The ScanIO-300LV connects to the UUT inputs and outputs with standard flat-cables that can optionally be terminated with test probes.
ScanPCI The ScanPCI boundary-scan based PCI and Compact PCI Card Tester provides a convenient method to test PCI and Compact PCI boards and their card-edge connectors.  The ScanPCI adds boundary-scan control and visibility to PCI and Compact PCI connectors that would otherwise be untestable or require expensive wiring adapter harnesses.  Even for those PCI and Compact PCI cards that have been designed with boundary-scan testing in mind, the circuitry between the PCI or Compact PCI card edge itself and the PCI interface devices, which typically have JTAG capability, is usually not fully boundary-scan testable. The Corelis ScanPCI™ provides a way to quickly and easily access these hard to reach connections and increase the boundary-scan test coverage of the Unit Under Test (UUT). The ScanPCI interfaces with a UUT that is either a 3.3V, 5V, or a Universal voltage device. Refer to the detailed data sheet of the ScanPCI for additional information.
ScanDIMMs The ScanDIMM™ Digital Tester modules are an easy to use tool for interconnect testing of memory DIMM sockets. Through the use of boundary-scan technology, the ScanDIMM Tester provides fully bi-directional test signals.  A boundary-scan Test Access Port (TAP) connects to a host computer which provides virtually unlimited memory depth for testing each of the DIMM socket(s) pins. DIMM sockets are often used for Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) and other types of memories and the ScanDIMM offers an accurate and easy to use mechanical and electrical solution for testing connections to the DIMM socket(s). Support is available for a number of DIMM formats including 184-pin DIMM, 168-pin DIMM, 144-pin SODIMM, 200-pin SODIMM, and 240-pin DIMM. Please refer to the detailed data sheets for the ScanDIMM products for additional information.
ScanPlus Chip Tester As devices densities increased to millions of gates with I/O pin counts exceeding 2,000, the test and verification of silicon devices became complex, cumbersome, and expensive. The use of high density packages, such as BGA, with their diminishing physical access to the pins, required that device vendors incorporate boundary-scan technology into their chips. The ScanPlus Chip Tester performs many of these same functions that more expensive device testers at a fraction of the cost, supporting components with up to 2040 I/O pins. The ScanPlus Chip Tester provides a powerful solution to the problem of boundary-scan testing and verification, even with the highest density and most complex semiconductor devices. Additionally, the ScanPlus Chip Tester can verify that an ASIC fully complies with the IEEE-1149.1 standard, the device runs at maximum TCK speeds, and the BSDL file matches the silicon.