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What is JTAG?
This overview provides a
brief overview of the JTAG architecture and the new
technology trends that make using JTAG essential
for dramatically reducing development and production costs.
The article also describes the various uses of JTAG and its application.
JTAG, as defined by
the IEEE Std. 1149.1 standard, is an integrated method for
testing interconnects on printed circuit boards that is
implemented at the IC level. The inability to test highly
complex and dense printed circuit boards using traditional
in-circuit testers and bed of nail fixtures was already
evident in the mid eighties. Due to physical space
constraints and loss of physical access to fine pitch
components and BGA devices, fixturing cost increased
dramatically while fixture reliability decreased at the same
time.
In the 1980s, the Joint Test
Action Group (JTAG) developed a specification for
JTAG testing that was standardized in 1990 as the
IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE
Std. 1149.1 standard was introduced (titled 1149.1a) and it
contained many clarifications, corrections, and
enhancements. In 1994, a supplement that contains a
description of the boundary-scan Description Language (BSDL)
was added to the standard. Since that time, this standard
has been adopted by major electronics companies all over the
world. Applications are found in high volume, high-end
consumer products, telecommunication products, defense
systems, computers, peripherals, and avionics. Now, due to
its economic advantages, smaller companies that cannot
afford expensive in-circuit testers are using JTAG.
The boundary-scan test
architecture provides a means to test interconnects between
integrated circuits on a board without using physical test
probes. It adds a boundary-scan cell that includes a
multiplexer and latches, to each pin on the device.
Boundary-scan cells in a device can capture data from pin or
core logic signals, or force data onto pins. Captured data
is serially shifted out and externally compared to the
expected results. Forced test data is serially shifted into
the boundary-scan cells. All of this is controlled from a
serial data path called the scan path or scan chain. Figure
1 depicts the main elements of a JTAG device. By
allowing direct access to nets, JTAG eliminates the
need for large number of test vectors, which are normally
needed to properly initialize sequential logic. Tens or
hundreds of vectors may do the job that had previously
required thousands of vectors. Potential benefits realized
from the use of JTAG are shorter test times, higher
test coverage, increased diagnostic capability and lower
capital equipment cost.
Figure 1 - Main Elements of a JTAG Device
The principles of interconnect
test using JTAG are illustrated in Figure 2. Figure
2 depicts two JTAG compliant devices, U1 and U2
that are connected with four nets. U1 includes four outputs
that are driving the four inputs of U2 with various values.
In this case we will assume that that the circuit includes
two faults: A short between Nets 2 and 3, and an open on Net
4. We will also assume that a short between two nets behaves
as a wired-AND and an open is sensed as logic 1. To detect
and isolate the above defects, the tester is shifting into
the U1 boundary-scan register the patterns shown in Figure 2
and applying these patterns to the inputs of U2. The inputs
values of U2 boundary-scan register are shifted out and
compared to the expected results. In this case the results
(marked in red) on Nets 2, 3, and 4, do not match the
expected values and therefore the tester detects the faults
on Nets 2, 3, and 4.
JTAG tool vendors
provide various types of stimulus and sophisticated
algorithms to not only detect the failing nets but also
isolate the faults to a specific nets, devices, and pin
numbers.
Figure 2 - Interconnect Test Example
JTAG Applications
While it is obvious that
JTAG based testing can be used in the production
phase of a product, new developments and applications of the
IEEE-1149.1 standard have enabled the use of JTAG in many other product life cycle phases. Specifically,
JTAG technology is now applied to product design,
prototype debugging and field service as depicted in Figure
3. This means the cost of the JTAG tools can be
amortized over the entire product life cycle, not just the
production phase.
Figure 3 - Product Life Cycle Support
To facilitate this product
life cycle concept Corelis, offers an integrated family of
software and hardware solutions for all phases of a products
life-cycle. All of these products are compatible with each
other, which protects the users investment.
Applying
JTAG for Product Development
Recent marketing drive for
reduced product size, such as portable phones and digital
cameras, higher functional integration, faster clock rates,
shorter product life-cycle with dramatically faster time to
market, has created new technology trends. These new
technology trends include increased device complexity, fine
pitch components such as SMTs, MCMs, and BGAs, increased
IC-pin count, and smaller PCB traces. This has created the
following problems in product development:
-
Many boards include
components that are assembled on both sides of the board.
Most of the through-holes and traces are buried and
inaccessible.
-
Loss of Physical Access to
fine pitch components such as SMTs and BGAs makes it
difficult to probe the pins and distinguish between
manufacturing and design problems.
-
A prototype assembly is
usually done by a small prototype assembly shop, in rush,
with lower quality control as compared to a production
house. A prototype generally will include more assembly
defects than a production unit.
-
When the prototype arrives,
a test fixture for the In-Circuit- Tester (ICT) is not
available and therefore manufacturing defects can not be
easily detected and isolated.
-
Small-size products do not
have test points which makes it difficult or impossible to
probe suspected nodes.
-
Many Complex Programmable
Logic Devices (CPLDs) and Flash devices (in BGA packages)
are not socketed and are soldered directly to the board.
-
Every time an engineer
selects a new processor or a different flash device, he
has to learn from scratch how to program the Flash memory
-
When a
design includes CPLDs from different vendors, the engineer
must use different in-circuit programmers to program the
CPLDs.
JTAG technology is
the only cost effective solution that can deal with the
above problems. In the last few years, the number of devices
that include JTAG has grown exponentially. Almost
every new microprocessor that is being introduced includes
JTAG circuitry for testing and in-circuit
emulation. Most of the CPLDs and FPGAs manufacturers such as
Altera, Lattice, and Xilinx, to mention a few, have
incorporated JTAG logic into their components
including additional circuitry that uses the JTAG 4-wire interface to program their devices in-system.
As the acceptance of
JTAG as the main technology for interconnect
testing and in‑circuit programming has increased, the
various JTAG test and in-system programming tools
have matured as well. The increased number of JTAG components and mature
JTAG tools, as well as other
factors that will be described later, provide engineers with
the following benefits:
-
Easy to
implement Design For Testability (DFT) Rules. A list of
basic DFT rules is provided later in this article.
-
Testability
report prior to PCB layout enhances DFT.
-
Find
packaging problems prior to PCB layout.
-
Little need for test points.
-
No need for test fixtures.
-
More control over the test process.
-
Quickly diagnose (with high resolution) interconnect problems
without writing any functional test code.
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Program code in flash devices.
-
Put design configuration data into CPLDs.
-
JTAG emulation and source-level debugging.
What JTAG Tools are needed?
In the previous paragraph we listed all the benefits that a
designer enjoys when using boundary-scan in his product
development. In this section we will describe the tools and
design data needed to develop JTAG test procedures
and patterns for in-circuit programming. We will use a
typical board as an illustration for the various
JTAG test functions needed. A block diagram of such
a board is depicted in Figure 4.
Figure 4 - Typical Board with JTAG Components
A typical digital board with
JTAG devices includes the following main
components:
-
Various JTAG components such as CPLDs, FPGAs, Processors, etc., chained
together via the boundary-scan path.
-
Non-JTAG components
(clusters).
-
Various types of memory
devices.
-
Flash Memory components.
-
Transparent components such
as series resistors or buffers.
The following will introduce
you to the major components of the various JTAG test tools available followed by a description of how to
test and program the above board.
A typical boundary-scan test
system is comprised of two basic elements: Test Program
Generation and Test Execution. Generally the Test Program
Generator (TPG) requires the netlist of the Unit Under Test
(UUT) and the BSDL files of the JTAG components.
The TPG automatically generates test patterns that allow
fault detection and isolation for all JTAG testable
nets of the printed circuit board (PCB). The TPG also
creates test vectors to detect faults on the pins of non-scannable
components such as clusters and memories that are surrounded
by scannable devices.
Corelis TPGs also provide the
user with a test coverage report, that allows the user to
focus on the non-testable nets and determine what additional
means are needed to increase the test coverage.
Test programs are generated in
seconds. For example when Corelis ScanPlusExpressTPG was
used, it took a 200MHz Pentium PC eight (8) seconds to
generate an interconnect test for a UUT with 4,090 nets
(with17,500 pins). This generation time includes netlist and
all other input files processing, as well as test pattern
file generation.
The test execution tool
provides means for executing JTAG tests and perform
in-circuit-programming in a pre-planned specific order
called a test plan. Test vectors files, which have been
generated using the TPG, are automatically applied to the
UUT and the results are compared to the expected values. In
case of a detected fault, the system diagnoses the fault and
lists the failures as depicted in Figure 6. Different test
plans may be constructed for different UUTs. Tests within a
test plan may be re-ordered, enabled or disabled, and
unlimited different tests can be combined into a test plan.
Corelis test execution tool (ScanPlus Runner) also includes
a test executive that is used to develop a test sequence or
test plan from various independent sub tests. These sub
tests can then be executed sequentially as many times as
specified or continuously if desired. A sub test can also
program CPLDs and Flash memories. For in-circuit programming
other formats such as SVF, JAM, J-Drive and STAPL are also
supported.
Figure 5 shows the ScanPlus
Runner main window. As can be seen, ScanPlus Runner gives a
user an overview of all test steps and the results of
executed tests. These results are displayed both for
individual tests as well as for the total test runs
executed. ScanPlus Runner provides the ability to add or
delete various test steps from a test plan, or re-arrange
the order of the test steps in a plan. Tests can also be
enabled or disabled, and the test execution can be stopped
upon the failure of any particular test.
To test the board depicted in
Figure 4, the user must execute a test plan that consists of
various test steps as shown in Figure 5.
Figure 5 - ScanPlus Runner Main Window
The first and most important
test is the scan-chain integrity test. The scan chain must
work correctly prior to proceeding to other tests and
in-system programming. Following a successful testing of the
scan chain, the user can proceed to testing all the
interconnects between the JTAG components. If the
interconnect test fails, the ScanPlus Runner will display a
diagnostic screen that will identify the type of the failure
(such as stuck at, Bridge, Open) and will list the failing
nets and pins as shown in Figure 6. Once the interconnect
test passes, including the testing of transparent
components, it makes sense to continue testing the clusters
and the memory devices. At this stage the system is ready
for in-circuit programming that usually is takes more time
compared to the testing.
Figure 6 - ScanPlus Runner Diagnostics Display
During the design phase of a
product, some JTAG vendors will provide design
assistance in selecting JTAG compatible components,
work with the developers to ensure that the proper BSDL
(Boundary-scan Description Language) files are used, and
provide advice in designing the product for testability.
Applying JTAG for Production Test
Production test, utilizing
traditional In-Circuit Testers that do not have
JTAG features installed, experience similar
problems that the product developer had and more:
-
Loss of Physical Access to
fine pitch components such as SMTs and BGAs reduces
Bed-of-Nails In-Circuit Testers (ICT) fault isolation.
-
Development of test fixtures
for ICTs has become longer and more expensive.
-
Development of test
procedures for ICTs has become longer and more expensive
due to more complex Ics.
-
Designer is forced to bring
out a large number of test points, which is in direct
conflict with his goals to miniaturize the design.
-
In-system programming is
inherently slow, inefficient, and expensive if done with
an ICT.
-
Assembling boards with BGAs
is difficult and subject to numerous defects such as
solder smearing.
Figure 7 shows a typical
production flow configuration that includes a JTAG tester that tests all the interconnects between the UUT
digital components and performs in-circuit programming of
all the CPLDs and Flash memories. Some test engineers
complement the JTAG test with an ICT that requires
simpler fixture primarily testing the analog components.
Figure 7 - Typical Production Flow Configuration
Following the ICT analog
tests, a comprehensive at-speed functional test is performed
before the product is shipped. However, in many cases, test
engineers are skipping the ICT test and moving from
JTAG interconnect test to a functional test that
includes thorough testing of the analog portion of the
product. The following are major benefits in using
JTAG test and ISP in production:
-
No need for test fixtures.
-
Integrates product
development, production test, and device programming in
one tool/system.
-
Engineering test and
programming data is reused in Production.
-
Fast test procedure
development.
-
Preproduction testing can
start the next day when prototype is released to
production.
-
Dramatically reduces
inventory management – no pre-programmed parts eliminates
device handling and ESD damage.
-
Eliminates or reduces ICT
usage time – programming and screening.
Production test is an obvious
area in which the use of JTAG yields tremendous returns.
Automatic test program generation and fault diagnostics
using JTAG software products and
the lack of expensive fixturing requirements can make the
entire test process very economical. For products that
contain edge connectors and digital interfaces that are not
visible from the JTAG chain, JTAG vendors
offer a family of JTAG controllable I/Os that
provide a low cost alternative to expensive digital pin
electronics.
Applying JTAG for Field Service
Once a product ships, the role of
JTAG does not end. Periodic software and hardware
updates can be performed remotely using the JTAG chain as a non-intrusive access mechanism. This allows Flash
ROM updates and reprogramming of programmable logic for
example. Service centers that normally would not want to
invest in special support equipment to support a product,
now have an option of using a standard PC or lap-top for
JTAG testing. A simple PC based JTAG controller can be used for all of the above tasks and also
double as a fault diagnostic system, using the exact same
test vectors that were developed during the design and
production phase. This concept can be taken one step further
by allowing an embedded processor access to the
JTAG chain. This allows diagnostics and fault
isolation to be performed by the embedded processor. The
same diagnostic routines can be run as part of a power-on
self-test procedure.
Obtaining the IEEE-1149.1 Standard
The IEEE Std 1149.1-1990 -
Test Access Port and Boundary-Scan Architecture, and the Std
1149.1-1994b - Supplement to IEEE Std 1149.1-1990, are
available from:
IEEE Inc., 345 East 47th
Street, New York, NY 10017, USA
1-800-678-IEEE (USA)
1-908-981-9667 (Outside of
USA)
You can also obtain a copy of the
standard from
http://www.ieee.org. |
