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ScanExpress JET™ Extending
Boundary-Scan with JTAG Emulation Functional Test |
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ScanExpress JET™ represents a
quantum leap in automatic circuit board testing. The JTAG
Emulation Test (JET) method extends your UUT boundary-scan
structural test coverage to virtually every signal on the board
that is accessible by the on-board CPU(s).
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ScanExpress JET utilizes
proprietary "JTAG Emulation Test" (JET) technology,
which uses a processor’s JTAG debug port to download and
control native processor code to perform at-speed
functional testing of the UUT. In addition to providing
test coverage for non-JTAG components, this technology
also allows programming of flash memories at their
fastest theoretical programming speed.
Highlights
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Figure 1.
ScanExpress JET UUT Typical Configuration
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ScanExpress JET Benefits
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Dramatically extends your UUT
structural test coverage with functional tests when UUT
includes a CPU with a JTAG debug/emulation port.
Multiple CPUs of the same or various types are also
supported.
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High-speed In-System CPU
assisted Flash programming saves you time in development
and production phases.
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Automatically generates
functional diagnostics tests in most cases, saving
months of coding and cost. To reduce mistakes, an
intuitive GUI guides the user through a logical sequence
of steps for constructing test steps from start to
finish.
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“C”-style script language
with a single-step capability assists in writing custom
tests and farther increasing the test coverage and
diagnostics. Also accepts pre-compiled user embedded
tests/code so that users can re-use existing diagnostics
code.
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Tests components’
functionality at-speed using test routines downloaded
via JTAG into CPU cache memory or RAM. Increases test
reliability and helps you diagnose failures when the
board does not boot.
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Same test station and GUI
for structural and functional testing and in-system
programming. Using a single JTAG controller for
boundary-scan, functional (emulation) tests, and
programming, greatly reduces costs and test fixture
complexity.
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Poor design-for-test (DFT)
in the circuit board can be overcome to some degree
because of coupling boundary-scan test and JTAG
emulation test in a unified test methodology.
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Extends at-speed coverage
beyond boundary-scan for:
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All CPU accessible
resources such as memories, CPLDs, FPGA, UARTS, etc.
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Non-scannable and analog
devices
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Memories with clock that
can not be controlled by boundary-scan
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I/O testing using external
equipment
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Reduces or eliminates the
use of In-Circuit Testers (ICTs) and Flying probes
saving you time and cost.
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Automatically constructs
test plans that can be executed directly via ScanExpress
Runner™ simplifying test plans generation and reducing
mistakes.
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Great tool for testing,
diagnosing, and troubleshooting ‘bone pile’ of
functionally inoperable UUTs that pass boundary-scan
tests but fail functionally.
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Growing list of supported
processors and peripherals.
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Helps detecting hard to
find power and ground structural defects by means of
running at-speed tests continuously and rigorously.
Special memory tests exercise UUT functionally to make
sure that Power and ground pins are properly connected
and do not cause intermittent failures. Typically power
and ground pins constitute 10-20% of high-density device
pin count and there is no easy way to test that these
pins are all connected. Further, there is no way to
detect open ground or power pins as often a device will
work OK even if several of its power and ground pins are
not connected. Often such a device, with some open
ground and/or power pins, may pass boundary-scan tests
and even power-up tests and this manufacturing defect
may go unnoticed until intermittent behavior is observed
in the field.
Table 1 depicts how combining the features of boundary-scan test
with JTAG Emulation Test increases the test coverage and reduces
test development.
Table 1 - Combining JTAG and Functional Test to Increase Test
Coverage
Who can benefit from using ScanExpress JET?
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Test engineers that want to
increase their boards’ test coverage and extend their
boundary-scan tests with at-speed functional tests.
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Design Engineers that need
to debug their prototype at-speed before test firmware and/or test fixtures are available.
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Firmware/software engineers
that want to save time and resources by creating
diagnostics tests automatically.
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Field application engineers
that want to verify if indeed a customer’s board is bad.
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Repair engineers who want
to find board failures quickly and at the lowest cost to
the customer.
Methodology
Corelis pioneered JTAG emulation and has shipped thousands of
JTAG emulators for many types of CPUs. Corelis is also the world
leader in boundary-scan test tools. Combining these two
technologies (that were developed for many years by Corelis)
into one product, provides customers with an integrated
development and execution test environment and with a single
point of contact and support.
The JET testing method depends on
the UUT having a JTAG-enabled processor (CPU) on-board. The CPU
dedicated JTAG Test Access Port (TAP) is generally routed to a
single emulation connector on the board. Other JTAG interconnect
scan chains may be connected to a different JTAG connector which
is used for boundary-scan testing.
The CPU debug TAP brings control
and visibility of the processor itself to the host. This is the
same TAP employed by JTAG emulators, such as the Corelis
CodeRunner tool, for software development and debug. Included
are access to the CPU register/control structures, attached
memory, and the ability to utilize the CPU debug
running/stepping facilities for testing.
The JET method harnesses the power
of the target embedded CPU to assist in the code download,
device programming and testing operations, at full processing
speed.
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Run
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Stop
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Step
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Write to Registers and
memory
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Read from Registers and
memory
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Exchange parameters with
the JTAG host
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Display CPU status
The host software uses these
features to download test/diagnostics routines into the CPU’s
cache memory and into the target memory. These routines execute
at speed and pass the test results to the host.
There is no need to modify the
on-board application software, typically stored in Flash
memory. The Flash memory itself can be similarly programmed
using the CPU as an algorithm expediter. This avoids the slower
wiggling approach of JTAG flash programming.
Connecting to
the UUT
A board may include a single JTAG
TAP that is dedicated to a specific CPU. This TAP is used for
software debug and/or boundary-scan test. A board may also
include multiple JTAG TAPs, one of them being used for software
debug and/or boundary-scan test and the other TAPs used for
boundary-scan test.
Corelis’ JTAG controllers support
multiple TAP configurations with a single controller. There is
no need to switch cables or use relays when moving from a debug
to test environment or switching from boundary-scan test to JTAG
emulation testing.
Figure 1 depicts connecting
Corelis’ NetUSB-1149.1/E™ JTAG controller to a board that
includes a CPU with a dedicated JTAG port, and additional
boundary-scan compatible devices chained into separate JTAG
ports.
Using ScanExpress JET
The ScanExpress JET tool is available as a stand-alone
application or as a plug-in to ScanExpressTPG. Functional tests
that are generated using ScanExpress JET are also compatible
with the ScanExpress Runner test executive. Figure 2
depicts the ScanExpress JET GUI.
Figure 2. ScanExpress JET GUI
The ScanExpress JET Integrated
Development Environment (IDE) consists of the following major
functions:
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Preparation — Several screens
that guide the user step by step on how to collect information
about the devices and setup of various test options. Following
these steps, the tool automatically produces the functional
test steps.
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Test Steps — Program that
executes the test steps that were previously created by the
preparation function.
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Reports — Analysis program to
view and calculate test coverage statistics
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Execution with the ScanExpress Runner option
— Invokes the ScanExpress Runner test executive to run both boundary-scan
and JET tests from a single test plan.
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JTAG Emulator — Invokes
the JTAG emulator program to enable
source level debugging of embedded software. Provides JET enhanced
peek/poke visibility of all CPU resources and registers,
including communications over I/O ports.
ScanExpress JET has the ability to
record all feature selections and file references to enable
recalling a given project. This serves as a mechanism to
quickly retest previous target boards as well as providing a
starting point for migrating similar test scenarios.
When operating as a plug-in to
ScanExpressTPG™, ScanExpress JET inherits the boundary-scan
environment parameters, including all settings and files of the
host application.
Preparation
This constitutes a set of
sequential screens which guide a user in selecting options and
declaring device specific parameters. It collects all the
information required to perform automatic testing using the JET
methodology. It also includes optional JTAG operations to
assure minimal board connectivity at the outset.
The major pieces of information required by the tool include:
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Devices — the tool requires
knowledge of CPU visible resources in the circuit. This
includes information such as memory device features such as
size, width of the addresses, etc. Much of this information
can be obtained automatically by the tool.
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Custom test scripts — user
developed test routines beyond those automatically created
by the tool.
The information collected becomes
part of the project, when saved.
Completion of the Preparation phase
results in the automatic creation of scripts, download routines,
and embedded tests steps required to perform specific board
testing.
Test Steps
The Test Steps screen lists the
test steps automatically created during the preparation phase
and provides controls to run tests on the target and view
results. The steps can be invoked individually, run in their
entirety or with an enabled subset and can even be looped.
Progress while the steps are
underway is also indicated.
This screen shows a PASS/FAIL
indication summarizing the overall outcome of all enabled test
operations. Detailed diagnostics of failure causes is
displayed.
Reports
The Reports function provides
access to test coverage statistics enabling the user to
determine the overall testability utilizing ScanExpress JET.
Included are merged coverage statistics showing how well testing
confirms board operability. Coverage information includes both
JET steps as well as legacy boundary-scan tests.
ScanExpress Runner
If
ScanExpress Runner is purchased, ScanExpress JET will
automatically pass the generated test files to ScanExpress
Runner. Clicking on the Runner icon in the shortcut pane on the
left side of the ScanExpress JET main window launches
ScanExpress Runner.
Using
ScanExpress Runner to execute boundary-scan tests in conjunction
with JET based tests provides a single test environment for a
complete test using both test methods. Verifying structural
integrity with JTAG interconnection test prior to running JET
functional tests results in better overall diagnostics during
failure conditions.
Figure
3 shows a test procedure within ScanExpress Runner
that contains both boundary-scan and JET functional tests.
Figure 3. ScanExpress Runner JTAG and JET Test Procedure
JTAG Emulator
ScanExpress JET includes an
optional JTAG emulator with multi-window support, allowing the
developer to view source code, assembly code, variables (both
local and global), memory, and register locations at the same
time.
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