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Boundary-Scan Description Language (BSDL)

The Boundary-Scan Description Language (BSDL) is a subset of VHDL (VHSIC Hardware Description Language) that describes how boundary-scan (JTAG) is implemented in a device and how it operates. Boundary-scan tools usually require that the user supply BSDL files for the devices being used in order to properly generate test vectors and perform in-system programming and functional testing.

To help you quickly locate BSDL files for your boundary-scan compatible devices, Corelis is providing the links below to popular semiconductor vendors and their BSDL files (if available).



The Boundary-Scan Description Language (BSDL) specification is contained in the IEEE 1149.1 standard which can be obtained from http://www.ieee.com/.  You can also read our Boundary Scan Description Language (BSDL) tutorial.

     

 

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Corelis offers free three-day training classes that include a boundary-scan tutorial and hands-on lab exercises using Corelis ScanExpress hardware and software.  The training class covers all aspects of boundary-scan testing using Corelis ScanExpress tools.

 
 

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BSDL File Validation

 
  Chip manufacturers and ASIC designers that implement boundary-scan in their silicon can utilize Corelis’ industry expertise to ensure their boundary-scan implementation meets the IEEE-1149.1 specification. Services include BSDL syntax and semantic checking, test vector generation and simulation, and final validation of all boundary-scan I/O pins on the device.
Learn More about BSDL File Validation
 
 

 
   
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