Resulted in Savings Exceeding $500,000 in Little More Than a Year
It was the high cost and long lead times for building In-Circuit Test (ICT) equipment that sent Mark Cooper, senior test engineer at Fujitsu, looking for circuit board testing alternatives. Production volumes of the company’s FLASHWAVE 4100 high-speed optical communications access device were substantial, but not enough to justify the $25,000 to $40,000 cost of an ICT test fixture and program for each type of board that required testing. The FLASHWAVE 4100 hardware configuration (See Figure 1) is a multi-slot “shelf” that accommodates up to 15 circuit boards, all interconnected through a common backplane. The boards perform a variety of functions from network control to multiplexing to interfacing for traditional SONET or multiple Ethernet LAN services, so there are 12 different card types, presenting Cooper with a complex manufacturing test operation combining fairly low volumes, but many different configurations. In addition, the cards themselves are complex – some double-sided – with a variety of programmable flash and CPLDs that need custom programming.
Figure 1. FLASHWAVE 4100 Multiservice Optical Access Solution
“We had been using ICT for our board test, but we were finding that we didn’t have the volumes to justify up to $40,000 for a program and fixture for each board when we were running only 100 boards through test in a year” said Cooper. “So that’s when we started looking at other options, and that’s when we ran across boundary scan.” Cooper reviewed vendors and was able to run trials with a few systems. His objective was to identify the system that was the easiest to learn and use, in terms of test development and debug, and yet powerful enough to test his complex boards. With that in mind, he chose the Corelis ScanPlus system with the ScanExpress Test Program Generator.
“It had a nice top-down flow. The wizards help when you first get started and the software tells you exactly what parameters it needs and the way it goes to generate the test program” said Cooper. “But in addition to testing, the system also allows us to fully program the devices on the cards, all in one cycle at one test station for a number of different combinations of flash and CPLDs.”
“We have boards that would take an hour and a-half to get all that done. And we had to do it through a bus structure that added time, rather than directly as we do now with boundary scan” Cooper said. “So we save money that way in an amount that I can’t even quantify.”
– Mark Cooper, Senior Test Engineer at Fujitsu
Test System Overview
Each test station interfaces to boundary scan (JTAG) test controller hardware hosted by a PC. Fujitsu chose the internal PCI-1149.1/Turbo interface card. A cable (up to 30 feet in length) connects to an access pod called the ScanTAP-4, that includes four test access port interfaces as shown in Figure 2. Fujitsu host application, invokes ScanPlus Runner software that runs the test plan and displays status and results on the PC. See Figure 3.
Figure 2. Corelis PCI-1149.1/Turbo JTAG Controller
Test vectors, in the form of Compact Vector Format (CVF) files, generated using ScanExpressTPG (test program generator), can be automatically executed and the results displayed and logged to a file. The system also supports other formats such as SVF, JAM, STAPL, and J-Drive. Test engineers can construct different test plans for different Units Under Test (UUTs) and reorder, enable, or disable tests within a test plan. An unlimited number of different tests can be combined into a test plan.
Figure 3. Host application displays ScanPlus Runner test results
Hardware, Labor and Lead Time Savings Quickly Add Up to Hundreds of Thousands of Dollars
Where Cooper once had to fund, build and staff an ICT station for each different card, he has consolidated his test operation to five test stations run by himself and one other person. Where he once had to put up with long lead times just to get a new ICT fixture and program built, he can now get ready to test a new card in a matter of hours. Since implementing the boundary scan test and programming system, Cooper has benefited from a range of savings that easily add up to an enormous return on the $175,000 total investment he has made in boundary scan:
- Since first using the system he estimates his savings at nearly $400,000 just in test fixtures and test program costs alone.
- Labor costs are cut because each ICT station required its own operator to “baby sit” the test in progress and reconfigure the station for different card specifications. By reducing staff from 12 to two, Cooper estimates $20,000 a month in savings from reduced labor costs. He has also connected the test system to lights that the ScanExpress software controls. Green (pass), yellow (need operator) and red (failure) lights let the operator know if any board tests need attention, so one person can operate half a dozen boundary scan stations.
- Far shorter lead times are needed to put new boards into production. Designing and building up a new ICT, test fixture and program typically took six-weeks. “With Corelis I can have a programming file developed, along with a full debug and test program in half a day. With that in place the whole test goes so smoothly” Cooper says.
- Test operators require less time to change from testing one configuration of a card to another compared to the manual process the ICT operators had to go through. Each change on the ICT stations meant manually changes to a number of specifications on the fixture and jumpers changes to fit the test points of different cards.
Important Tip for Implementing Boundary Scan
Cooper offers an important tip for making the transition to boundary scan testing. Copper suggests being open to design changes in your circuit cards that facilitate boundary scan testing and programming. A number of refinements in the design of the Fujitsu cards helped Cooper maximize the potential of his new system, “Corelis supplied a number of design recommendations and we immediately started giving that information back to our design guys and implementing the changes. Once we got our engineering team to buy into our design changes, things could not have gone smoother.”
More Value Waiting to Be Found
Cooper wants to further simplify his test stations by integrating the boundary scan connection into the backplane of the test shelf. The development will include emulating the Corelis boundary scan header, then tapping into unused pins in the backplane to bring the right signals, in the right states to reach the CPLDs, EPROMs and other devices on the board, and control the programming and test functions. He expects to complete the development in the next six months. The result will be an even easier hookup of devices under test, with a single connection to the test shelf, rather than plugging them into the shelf and then attaching another cable from the boundary scan test access port (TAP) to a separate boundary scan interface. Besides the tremendous cost savings, Cooper is meeting his ultimate goal: cutting the test time for his products to the bare minimum. “In this business it’s all about reduced handling, and improving throughput” Cooper sums up. “I don’t have to go out to the floor anymore to resolve false failure issues, and we don’t have a lot of intermittent issues like we did with ICT. I like that.”