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JTAG Boundary-Scan

Corelis JTAG Boundary-Scan Products

JTAG for Functional Test without Boundary-scan

IntroductionWe see a common theme with our JET application: users are looking for a solution where ICT is limited by physical access, when optical and mechanical solutions are not sufficient, and—an unfortunate case—when boundary-scan support is ei…

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JTAG Bypass Instruction

Using the BYPASS Instruction Introduction There are many misconceptions about the BYPASS instruction—most are related to what happens with the boundary-scan device IO pins after a device is placed in BYPASS. Often BYPASS is one of the first optio…

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PLD Tools: creating SVF, JAM, STAPL and other formats

Many vendors support creating of PLD files in SVF, JAM or STAPL format, but sometimes it’s not clear which formats should be used for a given vendor or given part. Based on our experience over the years, we’ve collected information about the file formats…

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Embedded System Success Story

IntroductionSystems based around a central and versatile microcontroller or processor run the risk of putting all the proverbial eggs in one basket. When the CPU is the only brain on the board, it will often be the only device with test capabilities such…

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Flash Memory Programming – Data File Formats

IntroductionScanExpress JTAG/Boundary-scan test execution tools with ISP capabilities (specifically ScanExpress Programmer & ScanExpress Runner) include capability to take in user data files and write them to Flash or other non-volatile memor…

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JTAG Chain: Multi-Voltage

IntroductionAs we see increased usage of mixed low voltage JTAG interfaces (3.3V, 2.5V, 1.8V, and even lower) on single PCB, it becomes important to consider different methods of managing multiple voltages. The solution usually comes down to two…

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SVF and STAPL/JAM: Adaptive FPGA Programming

IntroductionThere are two common file standards for programming FPGAs: SVF and STAPL/JAM. Most vendors can generate either type of file, but which should you choose? First we should look at a significant difference between the two: STAPL allows t…

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IntroductionThe HSWAP pin (also known as HSWAP_EN or PUDC) is commonly found on Xilinx FPGAs. This pin controls whether the FPGA’s user IO pins will have a pull-up resistor or float—when HSWAP is LOW, each IO pin will have an internal pull-up resis…

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Bypassing Boundary-Scan Devices

IntroductionOn occasion and due to incompatibilities, non-compliance, debugging, or various other factors related to the boundary-scan chain, it may be necessary to physically bypass a boundary-scan device and remove it from testing. The most com…

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Calculate Flash Programming Speed

IntroductionCalculating the theoretical Flash programming speed using boundary-scan can provide a good estimate for the time it will take and allows us to evaluate how specific factors will affect programming speed. To follow the Tips to Reduce F…

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