JTAG Boundary-Scan

Two part series Part 1: Internal Tests (this document) Part 2: External & Interactive Tests IntroductionWhile boundary-scan is an excellent way to test for structural faults, the relatively low speed often limits the usefulness for fu…

Two part series Part 1: Internal Tests Part 2: External & Interactive Tests (this document) IntroductionWhile tests that can simply run on a new prototype or are ideal, there are often cases where external hardware needs to be utilize…

Introduction In the search for higher test coverage, single pin nets (defined here as a net with only one node of any type) often come up and lead to questions: Should these pins be tested? Is there any coverage to be gained by including these pins…

IntroductionTAP adapter cables are often necessary to convert from the standard Corelis pinout to the TAP connector pinout of a particular target. The pinout may be Altera or Xilinx programming headers, CPU emulation headers, or other proprietary…

Programming serial buses using boundary-scan methods can be very slow; emulating a serial bus through boundary-scan means that we must scan the boundary-scan chain for each signal transition. The effective clock rate decreases with boundary-scan ch…

Continuing our discussion on FPGA & CPLD ISP using JTAG, we’ll look at a second case with FPGAs: indirect programming.Consider the case shown below. The configuration device is only connected to the FPGA, not to the JTAG chain. SPI Flash devi…

IntroductionIn-system programming (ISP) of CPLDs & FPGAs is a key application of JTAG. Most modern CPLDs & FPGAs include a JTAG port for programming and boundary-scan tests, and each vendor provides the software to generate an SVF or STAPL/…

You may have noticed in Corelis' Design for Test Guidelines a note on PLL clock buffers, and why they should be avoided when dealing with boundary-scan tests. PLLs contained in clock distribution ICs generally will not function correctly with a c…

IntroductionMany FPGAs in their preconfigured state include relatively strong internal pull-up/pull-downs, often in the 4.7k-ohm range or lower. If a weak pull-up/pull-down resistor is attached to such a pin, there is risk that the pull-up/pull-d…

Termination of the scan chain signals, including both data and clock lines, is often an afterthought in board design but can have a strong effect on signal integrity. We like to stress in ourDFT Guidelines, documentation, and discussions that sig…