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ScanExpress JET Peripheral Tests – Part 1

Two part series Part 1: Internal Tests (this document) Part 2: External & Interactive Tests IntroductionWhile boundary-scan is an excellent way to test for structural faults, the relatively low speed often limits the usefulness for fu…

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ScanExpress JET Peripheral Tests – Part 2

Two part series Part 1: Internal Tests Part 2: External & Interactive Tests (this document) IntroductionWhile tests that can simply run on a new prototype or are ideal, there are often cases where external hardware needs to be utilize…

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Testing Single Pin Nets with JTAG/Boundary-scan

Introduction In the search for higher test coverage, single pin nets (defined here as a net with only one node of any type) often come up and lead to questions: Should these pins be tested? Is there any coverage to be gained by including these pins…

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JTAG TAP Adapter Cables

IntroductionTAP adapter cables are often necessary to convert from the standard Corelis pinout to the TAP connector pinout of a particular target. The pinout may be Altera or Xilinx programming headers, CPU emulation headers, or other proprietary…

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Device Programming: JTAG, SPI, and I2C

Programming serial buses using boundary-scan methods can be very slow; emulating a serial bus through boundary-scan means that we must scan the boundary-scan chain for each signal transition. The effective clock rate decreases with boundary-scan ch…

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JTAG Programming of CPLDs & FPGAs: Indirectly Programmable Configuration Device

Continuing our discussion on FPGA & CPLD ISP using JTAG, we’ll look at a second case with FPGAs: indirect programming.Consider the case shown below. The configuration device is only connected to the FPGA, not to the JTAG chain. SPI Flash devi…

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JTAG Programming of CPLDs & FPGAs

IntroductionIn-system programming (ISP) of CPLDs & FPGAs is a key application of JTAG. Most modern CPLDs & FPGAs include a JTAG port for programming and boundary-scan tests, and each vendor provides the software to generate an SVF or STAPL/…

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JTAG Boundary-scan Tip: Phase-locked Loops (PLLs) in Clock Buffers

You may have noticed in Corelis' Design for Test Guidelines a note on PLL clock buffers, and why they should be avoided when dealing with boundary-scan tests. PLLs contained in clock distribution ICs generally will not function correctly with a c…

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JTAG Boundary-Scan Test Tip: Strong Pull-ups on FPGAs

IntroductionMany FPGAs in their preconfigured state include relatively strong internal pull-up/pull-downs, often in the 4.7k-ohm range or lower. If a weak pull-up/pull-down resistor is attached to such a pin, there is risk that the pull-up/pull-d…

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Scan Chain Signal Termination

Termination of the scan chain signals, including both data and clock lines, is often an afterthought in board design but can have a strong effect on signal integrity. We like to stress in ourDFT Guidelines, documentation, and discussions that sig…

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