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JTAG Boundary-scan Tip: Phase-locked Loops (PLLs) in Clock Buffers

You may have noticed in Corelis’
for Test Guidelines
a note on PLL clock buffers, and why they should be
avoided when dealing with boundary-scan tests. PLLs contained in clock
distribution ICs generally will not function correctly with a clock input that
neither maintains a constant frequency nor operates in the correct frequency
range. This applies to both the JTAG clock (TCK) and to synchronous device clock
pins, such as those found on SDRAM.

However, all hope is not lost! Many buffers have a method of disabling or
bypassing the PLL. For boundary-scan testing this mode should be used whenever
possible, and the clock distribution device should use a transparent model in
ScanExpress TPG. Some common methods for dealing with PLLs include:

  • PLL disable pin, such as a test pin.
  • Mode pins, which include a bypass mode. Sometimes this is stated by
    saying the “reference” is applied to the outputs.
  • Applying a different voltage (sometimes no power) to a power pin,
    usually the PLL power pin.
  • Please refer to the device data sheet to determine if and how the
    internal PLL can be disabled.

For example, compare the popular Cypress CY2305 & CY2309 clock
buffers (data sheet available from the Cypress website at

). See table 2 of the referenced data
sheet: CY2309 includes select input pins not available on the CY2305,
adding a PLL shutdown mode in which the output source follows the reference
clock, allowing the clock buffer to be treated as a transparent device during
boundary-scan tests.

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