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Using Freescale TAPs for Early Boundary Scan Testing – VIDEO

Corelis has integrated Freescale TAP probes into our boundary scan software. By doing this, you can utilize pre-written tests for specific Freescale development boards to check out your hardware, debug issues, and as a starting point for your own custom boards. Simplify your development AND jump-start your testing.

How did Corelis accomplish the feat of conducting hardware tests with an emulator probe normally used for software debugging?  There are several factors that enabled this ability.

First, Corelis’ Runner-Lite leverages capabilities already baked into the debug interface and the components. Given that the JTAG interface is often used to debug embedded programs and load code into firmware, it is easy to get the mistaken impression that its sole purpose is for debugging. However, the JTAG interface, as its acronym states, is also about testing. Originally conceived as a means to examine the operation of the interconnects between integrated circuits on multi-layer boards, JTAG evolved into the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification. This specification, among other things, describes a number of instructions that JTAG uses to test the logic cells (the boundary) that manage the interface pins of a part. In addition, a JTAG-compliant part must implement a boundary-scan register that controls the pin signals directly and stores information about the responses to the generated signals. Given the expense required to do unit test, many semiconductor manufacturers—including Freescale—build support for the boundary-scan commands and the boundary-scan register into their silicon. Boundary-scan testing also helps with quality control since a chip that flunks a boundary-scan test gets sent to the scrap heap rather than to a customer.

Second, Freescale TAP run controllers provide an extensive “raw” JTAG mode that implements all the features of the JTAG specification, not just the portions used for debugging. The Freescale USB TAP (Figure 1) and Gigabit TAP implement this important capability, and as such both can be used for boundary-scan tests.

Figure 1. A Freescale USB TAP with built-in support for boundary-scans.

The third factor behind implementing boundary-scan support is Freescale’s own software sauce, its CodeWarrior Connection Server (CCS). The CCS is a software driver that abstracts the JTAG interface and TAP run controller logic so that all of these functions are managed through a device-independent API. The CCS enables software tools such as the CodeWarrior debugger or Corelis’ Runner-Lite to communicate transparently to an MPU or other JTAG-compliant component through different types of run controllers that can be using different connection interfaces. For example, the CCS can readily direct debugger or boundary-scan commands to a TAP run controller whether it is connected the workstation by a USB cable (the USB TAP) or an Ethernet network connection (the Gigabit TAP). Or, two different CodeWarrior debuggers running on the same workstation can, via the CCS, issue command and control instructions to dissimilar cores on the same multicore processor. As an example of this, the CodeWarrior for StarCore DSPs tools and CodeWarrior for Power Architecture tools can be used to simultaneously debug embedded code executing on the Power Architecture e500 core and the StarCore SC3850 core that make up a QorIQ Qonverge BSC9131. The fine-grained level of control provided by the CCS for such close-to-the-silicon hardware functions, along with the previously-mentioned raw mode in the TAP probes, makes boundary-scan testing possible.

In order to issue boundary-scan commands and obtain a view of the boundary-scan register, Corelis needed access to detailed information about the CCS API. Freescale documents this information and an SDK to access the API in a CCS Connection Kit. Corelis, in close collaboration with Freescale, used the CCS Connection Kit to access the low-level JTAG communications required by its Runner-Lite test application. See Figure 2.

Figure 2. Block diagram showing board component testing using Runner-Lite and a Freescale TAP run controller.

Test Plans

Runner-Lite uses test plan files to perform the structural and functional checks on a board. These test plan files specify the characteristics of the parts under test and the operational steps used to implement the various tests. The files are sophisticated enough to describe a target board’s components and bus architecture in its entirety. The information in these files is critical to Runner-Lite’s operation, and as a consequence, the application requires a test plan file for a board in order to test it.

Sequences of operational checks can be combined into sub-tests known either as “cases” or “steps”. Test steps can be enabled or disabled as needed to modify a test plan. Runner-Lite provides a large suite of steps that can completely test a board. For example, a processor test step directs a boundary-scan check on the MPU. A basic test step applies signals on the interconnects to memory (RAM and flash) and validates their integrity. Other test steps in the test plan file can evaluate the interconnects to various board peripherals. Runner-Lite also supports JTAG Embedded Test (JET) where code can be loaded onto the MPU that then runs the board peripherals through their paces at-speed for a more thorough integrity check.

Using the steps stored in the test plan file, Runner-Lite transmits the specified boundary-scan test patterns for the board components, and retrieves the results. It then displays any problematic interconnects in a diagnostic window (Figure 3). Runner-Lite even has the capability to display problem locations on a scanned image of the board. It can also execute hardware tests encoded in industry standard formats such as SVF, JAM, and STAPL.

Figure 3. Failure results screen

Being able to perform boundary-scan tests early in the product development cycles has significant benefits. Some of these are:

  • Reduce or eliminate delays in software development due to hard-to-trace hardware problems
  • Shorten project cycle times because hardware problems or design errors are detected earlier
  • Assist in board bring-up
  • Design errors are caught earlier, which presents a window of opportunity to suggest improvements and test them

As a result of the early diagnostic checks and testing provided by Runner-Lite, the final design turned over to manufacturing has a higher degree of confidence.

Best of all, Runner-Lite’s boundary-scan capability does not require the purchase of anything other than the Freescale TAP run controller—something you would do anyway to debug the product software and program its firmware—and a Corelis test plan file. The ability to do boundary-scan testing using the same TAP run controller for software development is a win-win situation for developers. How often does that happen?

Still need convincing? Runner-Lite is a complimentary download with registration from the Corelis web site. Corelis is working closely with Freescale to generate test plan files for other QorIQ-based boards in the near future. For those of you designing your own QorIQ-based boards and are considering boundary-scan testing for them, you can contact us to evaluate our more advanced testing software such as ScanExpress and TestGenie. For third parties interested in having their own software make use of the Freescale’s CCS to access JTAG or low-level board functions, contact Freescale on how to obtain the CCS Connection Kit.

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