ScanExpress TPG

Test Pattern Generator Software

To deliver a product meeting the highest standards of quality and reliability, design engineers and test engineers alike must maintain test capabilities throughout the entire product life cycle, from prototype to manufacturing. Automation in test generation is essential to ensure that tests keep up with the rapid development of modern products.

The ScanExpress TPG™ Intelligent Test Pattern Generator Software provides a highly advanced, automated boundary-scan test design environment—perfect for quick and efficient creation of complete boundary-scan tests for all IEEE-1149.1 and IEEE-1149.6 compliant circuit boards.

Features

  • An intuitive wizard guides the user through the construction of complete test procedures

  • Automatically generates test patterns for infrastructure, interconnect, memories, FIFOs, clusters, and resistors using proven, mature boundary-scan test algorithms

  • Test management functions for creating project revisions and test variations within a single parent test project

  • Detects and supports industry standard CAD netlist formats

  • Identifies the boundary-scan chain order and draws a graphical representation of the boundary-scan chain

  • Finds and classifies all resistors and resistor packs as either pull-up, pull-down, series, differential termination, or non-testable resistor types

  • Complex script language with integrated debugging environment assists in writing custom boundary-scan test steps

  • Constructs test plans for integration into the ScanExpress Runner™ test execution sequencer (sold separately)

  • Assembles detailed fault coverage analysis reports for use with the ScanExpress DFT Analyzer™ (sold separately)

  • Single Integrated Development Environment (IDE) for all JTAG applications simplifying test development, execution, and analysis

  • Complies with IEEE standards 1149.1 and 1149.6

  • Compatible with Microsoft Windows 7, Windows 8/8.1 and Windows 10

The ScanExpress TPG Interface

TPG leverages a versatile IDE to provide automation and guidance for all users without sacrificing customizability and power. Development consists of two distinct phases: Preparation and Generation. By guiding the user through the process of defining the UUT, TPG creates a comprehensive boundary-scan test in a matter of minutes.

ScanExpress Runner Gang

The Preparation Phase

ScanExpress TPG test development begins by gathering details about the UUT from the user in an interactive session through a series of steps. The intelligent preparation engine assists the user with assigning input files, identifying special nets, and modeling devices on the UUT.

TPG features a comprehensive and ever-expanding library of device models for popular devices including resistors, buffers, RAM, Flash, and many more. The automatic association features quickly find models every step of the way.

ScanExpress TPG optionally logs all part numbers and associated data within each project for re-use in additional projects, further reducing new test development time.

The Test Generation Phase

The Test Generation phase provides tools to further personalize, fine tune, and generate test files. The user is free to directly modify the input files, add customized test steps, and utilize TPG’s advanced “C”-style boundary-scan scripting language with integrated debugging environment to edit or create adaptive and interactive test steps.

When the user is ready to compile tests, the state-of-the-art automatic test pattern generation (ATPG) engine creates test steps ready-to-run in the ScanExpress Runner™ test execution sequencer.

BusPro-S SPI Bus Host Adapter

BusPro-S Tutorial

The BusPro-S SPI Tutorial provides an introduction to the SPI bus, including basic bus options, common transaction formats, and example SPI Exerciser command code.

Applications

SPI Protocol Hardware Debug

Generate SPI bus traffic and interface with peripheral components.

In-System Programming

Read, erase, program, and verify SPI Flash Memories and EEPROMs within the system using the SPI interface.

Benefits

Save time and effort at the repair station by visually identifying probable fault.

Decrease expertise requirements with easy-to-read, graphical fault indicators based on advanced boundary-scan diagnostics.

Ordering Information

Part Number 90200

Need Assistance?

We’re here to help!

If you would like assistance with implementing JTAG testing in your design, or you are simply short of resources, our talented and experienced engineering staff can help you with all your JTAG needs.

IEEE-1149.6 Support

For ScanExpress Tools

The ScanExpress automatic test development suite provides full support for the IEEE-1149.6 standard by scanning a PCB netlist to detect, model, and classify devices involved in AC-coupled circuit topologies.

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