Capacitors – Part 2 of Test Coverage Q & A

Test coverage of capacitors in boundary-scan are an interesting topic—after all, isn’t boundary-scan capable of digital signaling only? Sure the IEEE-1149.6 standard added the capability to test across coupling capacitors, but what about capacitors connected to power or ground?

In this article we’ll take a look at some interesting questions regarding test coverage of nets connected to capacitors.

Q: Capacitors on Power nets are labeled with PARTIAL coverage; why?

A: If a net defined as a power or ground net has a connection to a boundary-scan pin which can sense the net, then TPG automatically adds constraints to sense ‘high’ or ‘low’ on this net. This sensing capability on the net makes it classify as a PARTIAL tested net.

Note: Keep in mind that designs often include power nets which are not critical to basic board operation; these nets are produced from the main power, meaning that even if these power nets were not ‘on’, the board may still be operational in some areas and boundary-scan control of the devices may be working. Boundary-scan tools do not in general differentiate between critical and non-critical power nets.

Once a Net has been classified with PARTIAL test coverage, TPG also adds this level of coverage to any device pin on that net. Thus, all the capacitors that connect to power nets will be classified with PARTIAL coverage on their pins.

Q: OK, but what does PARTIAL mean in this specific case? What is tested?

A: It should be made clear that PARTIAL coverage in the device coverage report does not mean that the capacitor is tested for presence—after all, the test is likely to have the same result regardless of the capacitor being populated or not unless the capacitor is critical to board operation. The partial coverage indicated in the report simply means that the capacitor is connected to nets with partial coverage.

Take, for example, the case shown in Figure 3 below.

Figure 3. Diagram of system with capacitors attached to Vcc and ground.

In this case, pin U3.1 will attempt to sense a ‘high’ level because it is connected to Vcc. Pin U3.2 will attempt to sense a ‘low’ value because it is connected to ground. Thus, the software considers Vcc and ground to be partially tested nets and, as such, all pins on these nets have a minimum of partial coverage.

A short across either capacitor C1 or C2 will have no direct effect on U3 pins 1 and 2, though if this capacitor is critical to board operation it may cause test failures not easily traced to the capacitor. The same can be said of an open fault on one of the pins or a missing capacitor. A short from the Vcc side of C1 to ground may or may not cause U3.1 to sense ‘low’, but considering that it would be a short from power to ground, it may show up as a catastrophic failure in boundary-scan tests.

If it is undesirable to count capacitor pins as covered by boundary-scan when evaluating test coverage, those capacitors can be easily removed from the testing reports using the Report Edit function of the ScanExpress DFT Analyzer tool.

Q: What about Inductors? Can I consider inductors to be transparent for test coverage?

A: Much of the same information applies to inductors connected to boundary-scan pins. However, inductors with boundary-scan pins on either side can often be tested for opens, since they will pass DC current.

Capacitor pins connected to power or ground nets that also have boundary-scan sense pins will be labeled with partial coverage, due to the definition of pin partial coverage. In the next part of this Q & A, we’ll take a look at how Flash programming affects test coverage.

Published On: January 17, 2013Categories: Corelis Boundary-Scan Blog, JTAG Boundary-Scan

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