Corelis Introduces a High Performance Boundary-Scan (JTAG) Controller with Network Connectivity
New LAN-based intelligent Boundary-Scan Controller
provides remote boundary-scan testing capabilities
Cerritos, CA, December 9, 1996 — Corelis Inc., today introduced a high performance, self contained and network enabled, intelligent boundary-scan controller. The Net-1149.1 integrates the power of a local area network into the entire boundary-scan development, production, and test process. It provides an intelligent interface, with memory-behind-the-pin architecture, between any PC or workstation that has networking support for TCP/IP protocol over Ethernet.
The Net-1149.1 provides four (4) independent IEEE-1149.1 (JTAG) Test Access Ports (TAPs) with programmable JTAG clock rates up to 35 MHz, and includes 16 general purpose I/O lines, individually controlled, for remote control and sense. The Net-1149.1 serializes to each of the ports boundary-scan instructions and test vectors which are previously loaded by the host over the network. The unit under test (UUT) responses are stored in the on-board 4M bytes (expandable to 16M bytes) of dual-port memory and uploaded to the host for further analysis.
A high performance 32-bit RISC processor receives data from the UUT and prepares only the relevant information for the host. This assures maximum test throughput and enables the host to be free of overhead in serializing the boundary-scan data. A Scan Function Library is supplied with the product to allow the end user to create powerful test programs.
“Boundary-scan test vectors developed with automatic boundary-scan test pattern generators can be loaded to the Net-1149.1 and applied to the unit under test. For potentially long tests, such as Built-In-Self-Test, it is desirable that the host be free to perform other tasks while testing is in progress.” said Menachem Blasberg, president of Corelis, Inc. “The standard 4M byte (optionally 16M byte) pattern buffer allows sufficient vector depth to handle test applications involving complex ASICs and highly populated boards without the need to reload the memory.”
To compensate for propagation delay in long test cables to the Unit Under Test (UUT), a programmable delay can be enabled between the active Test Clock (TCK) edge and the sampling of the UUT’s TDO data. This reduces the possibility of sampling errors caused by long cables or internal delays when running at very high clock rates. Additional flexibility is provided by provisions for UUT synchronization, programmable event detection, and pause waiting. Combined with the 16 BI-directional and individually programmable digital I/O lines, the Net-1149.1 provides unparalleled flexibility.
Corelis is a world leader in the field of boundary-scan (JTAG) testing, microprocessor development tools, and VXIbus test instruments. Corelis also provides various engineering services and is well known for its outstanding customer support.