by Corelis Inc. Corelis Inc.

Corelis Introduces ScanPlusDFT Analyzer that Enables Sophisticated Boundary-Scan Test Coverage Reporting

ScanPlusDFT Analyzer dramatically increases Boundary-Scan test
coverage and reduces test program development time

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Cerritos, CA, January 15, 2002 — Corelis Inc., introduced today a new boundary-scan Design-for-Test (DFT) tool, ScanPlusDFT Analyzer, which generates test coverage summary and detailed reports for all the nets and pins on the board under test.  Boundary-Scan, also known as JTAG, is an embedded IC technology for testing digital circuit boards and components that has been standardized as IEEE Std 1149.1.  Until now, finding precisely the test coverage of boards that include boundary-scan components was a daunting task. There was no automatic way to quantify increase in test coverage when more test steps, such as memory tests, were added to the test plan. Now the use of ScanPlusDFT  Analyzer reduces the test coverage analysis time to seconds. It also precisely classifies nets and pins by level and type of testability coverage.

The ScanPlusDFT Analyzer analyzes for testability boards and systems that include a mix of boundary-scan and non-boundary-scan devices, and assists design and test engineers to increase fault coverage and reduce boundary-scan test program development time.

The ScanPlusDFT Analyzer intelligently merges various testability reports generated by the ScanPlusTPG  test program generator and provides summary and detailed test coverage reports for the board. The combined test coverage reports help engineers to maximize the use of boundary-scan and reduce the need for “nails” access to nets and pins of the board under test.

The ScanPlusDFT  Analyzer is generally used after schematic capture and before PCB CAD layout. At this stage of product development, ScanPlusDFT Analyzer can create a comprehensive test coverage report that identifies all the boundary-scan net and pins and classifies them as completely tested, partially tested, and not-tested. The report also includes recommendations where to add test points (pads) for physical “nails” access if additional test coverage is required.

“The use of the ScanPlusDFT Analyzer software helps engineers to increase dramatically their boundary-scan test coverage prior to submitting their design to board layout,” said Steven Hartman, product marketing manager for Corelis’ ScanPlus product line. Mr. Hartman added: “Having higher test coverage ultimately results in reducing time to market, lowering test costs, and improving product quality.”

Corelis Inc., offers a broad line of boundary-scan software and hardware products for interconnect testing, in-system programming of Flash memories & CPLD’s, JTAG emulation and debugging. It includes a full range of IEEE-1149.1 boundary-scan testers for the ISA, USB, PCI, PCMCIA, LAN, PXI and VXI busses. Corelis also provides various engineering services and is well known for its outstanding customer support.

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