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Debug a Dead Board

Debug a Dead Board

Learn how to “Debug a Dead Board” using Corelis ScanExpress JTAG/boundary-scan and ScanExpress JET products in conjunction with a Blackhawk JTAG emulator.

What is a Dead Board?

“Dead” generally refers to a board that does not respond, initialize or power-up to an expected state. Failure modes can typically be broken down into two categories: hardware and software.

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Prototype Bring-up & Debug Cycle

  • Visually check correct component installation
  • Verify no shorts on power rails to ground
  • Apply current-limited power to the board, ensure nothing gets hot, verify voltage levels
  • Load basic boot code and functional code to verify CPU and peripheral operation

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Existing Test Tools

  • There are many tools that can assist in the debug process

  • Having the most efficient tool for the job saves engineering time

  • Knowing which tool to use at the right time is key

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Corelis Structural & Emulation Test Tools

  • There Corelis directly replaces many traditional debug tools by providing automated test generation and low level diagnostic information saving valuable engineering time and effort
  • Structural testing identifies physical faults such as broken circuit traces, solder bridges and cold solder joints
  • Emulation testing verifies DSP operation and exercises peripheral interfaces at intended design speeds

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mainbuildingblocksofaJTAGde1 - Debug a Dead BoardJTAG Architechture

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Main Building Blocks of a JTAG Device

  • JTAG Interface Pins
  • Test Data Registers
  • Instruction Register
  • TAP Controller

JTAG Scan-Chain

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JTAG Test Vectors

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Benefits of JTAG

  • JTAG provides the capability to test interconnects on a PC-board without physical test probes or test fixtures
  • Does not require the board to be in a bootable state for fault diagnostics
  • JTAG allows In-System Programming of devices such as Flash, CPLDs, FPGAs and Serial EEPROMs+

JTAG Advantages

  • Automated test development for DSP initialization, memory and flash
  • Device level diagnostics
  • Customized diagnostic messages
  • JET rigorously exercises allexternal memory locations before execution of any boot code
  • Test vectors can be reused in production

JTAG and JET Fault Coverage

  • JTAG Pin Connectivity; Noisy Signals
  • Opens, Shorts & Stuck-At Conditions
  • DSP Initialization
  • Component Discovery and Identification
  • Bad Memory Locations
  • Flash Communication Problems
  • Timing Problems

JTAG Emulation Test

emulationtest - Debug a Dead Board

JET uses a DSP’s JTAG debug port to perform:

  • DSP initialization

  • At-speed functional testing of DSP peripherals (memory, I/O)

  • In-System-Programming (ISP) of flash devices

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JET Benefits

  • Does not require the board to be in a bootable state for fault diagnostics
  • Embedded tests are downloaded and run from on-chip DSP memory at-speed
  • Provides testability on all DSP addressable components by exercising their functionality
  • In-system programming at theoretical speeds reduces time waiting for code to download

JET Advantages

  • Automated test development for DSP initialization, memory and flash
  • Device level diagnostics
  • Customized diagnostic messages
  • JET rigorously exercises allexternal memory locations before execution of any boot code
  • Test vectors can be reused in production

Combining JTAG and JET

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JTAG & JET Fault Coverage

  • JTAG Pin Connectivity; Noisy Signals
  • Opens, Shorts & Stuck-At Conditions
  • DSP Initialization
  • Component Discovery and Identification
  • Bad Memory Locations
  • Flash Communication Problems
  • Timing Problems

Case Study – Complex TI Target

  • Board includes twenty-six TI DaVinci processors
  • Board includes other JTAG and non-JTAG components
  • JTAG components include a PowerPC CPU and two FPGAs
  • Corelis JTAG tools are able to perform full interconnect and basic memory pin testing
  • JET to the rescue…JET emulation testing identified crosstalk and signal integrity issues on SDRAM memories that JTAG scans did not detect

TI board - Debug a Dead Board

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