by Corelis Inc. Corelis Inc.

Corelis Unveils a High-Performance 2040-Pin Chip Tester Specifically Tailored for Custom ASIC Boundary-Scan Validation

The new ScanPlus Chip Tester™ provides up to 2,040 independent I/O pins for boundary-scan verification of large-scale ASIC and other high density integrated circuits.

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Cerritos, CA, July 16, 2003 — Corelis Inc., recently unveiled a new high performance boundary-scan test system that allows boundary-scan testing and verification of large-scale ASIC and other high density integrated circuits.  With up to 2,040 independent test points, the ScanPlus Chip Tester™ provides abundant test point coverage for even the highest density BGA packages.  Its ability to verify the tested device’s compliance to the IEEE-1149.1 specification, and the accuracy of the BSDL file description against the actual silicon, provides chip integrators with an invaluable tool when debugging silicon.  The ScanPlus Chip Tester™ was specifically developed for today’s most demanding applications including Multi-Chip-Modules (MCM) and system-on-chip (SOC) designs.

The Corelis ScanPlus Chip Tester™ is an intelligent boundary-scan tester that is used in conjunction with the PCI-1149.1/Turbo boundary-scan controller.  Utilizing this high-speed controller, the ScanPlus Chip Tester™ achieves TCK speeds up to 80 MHz.  The ScanPlus Chip Tester™ also offers excellent flexibility due to its four banks of adjustable voltage levels, separate power regulation of tester and target, four analog test channels, three programmable clock generators and on-board memory.  Boundary-scan test vectors developed with Corelis’ ScanPlusTPG Test Program Generator can be executed directly on the ScanPlus Chip Tester™.

Until now, very expensive semiconductor testers and test fixtures were used to perform device testing and boundary-scan verification functions.  The ScanPlus Chip Tester™ performs many of these same functions at a fraction of the cost.

“The ScanPlus Chip Tester provides a simplified integration path for boundary-scan validation on large-scale ICs” said Jim Rodgers, Technical Marketing Engineer at Corelis, Inc.  “Its scalable architecture simplifies and lowers the cost of the fixtures needed to test devices with BGA packages that include up to 2040 pins.”

The ScanPlus Chip Tester™ is available from stock.

Boundary-scan is an embedded IC technology for in-system programming and testing of digital circuit boards and components that have been standardized as IEEE Std 1149.1.  Corelis’ ScanPlus Boundary-scan tools include hardware and software products offering exceptional ease-of-use combined with advanced technical innovation.

Corelis Inc., offers a broad line of Boundary-scan software and hardware products for interconnect testing, in-system programming of Flash memories, CPLDs, FPGAs, JTAG emulation and debugging. It includes a full range of IEEE Std 1149.1 Boundary-scan testers for the ISA, PCI, PCMCIA, LAN, USB, cPCI/PXI and VXI busses. Corelis also provides various engineering services and is well known for its outstanding customer support.

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