Successful JTAG testing depends on careful board-level design. These tips will help designers improve the testability of their boards.
Schematic Design Considerations
During schematic design, careful attention must be paid to device selection, scan chain design, the TAP interface connector, and board-level design-for-testability rules.
JTAG Device Selection / Identification
Use JTAG components whenever possible; more JTAG components means more pins in the system that can participate in tests.
Ensure that device datasheets indicates IEEE-1149.1, JTAG or boundary-scan compliance.
High pin count BGA or surface mount device devices are good candidates for JTAG testing. This includes FPGAs, CPLDs, CPUs, and DSP.
Look for pin names TCK, TMS, TDI, TDO and TRST_N. These signals often indicate JTAG compatibility.
Verify that a boundary-scan description language (BSDL) file is available from the device manufacturer.
JTAG devices are available from many IC vendors, including Atmel, Broadcom, Cypress, IDT, Intel, Lattice, Marvell, Micron, NXP, QLogic, Samsung, ST Microelectronics, TI, Xilinx, and many more.
Design boundary-scan into the product, not as an afterthought
Design engineers must think ahead about testing. Waiting to consider how a product will be tested testing until after it is complete will lead to failure.
Utilize DFT guidelines prior to and during board layout.
Identify up front whether devices have BSDL files available and ensure they have been tested.
Consider the initial power-up or reset state of board. To ensure that scan chain will be operational when power is applied, compliance enable pins must be terminated properly. Additionally, devices like CPLDs that control power logic or scan paths must remain in BYPASS during tests, and the TRST* pin must be high during JTAG tests.
Tri-state or disable non-boundary-scan devices to prevent them from interfering during boundary-scan tests. If possible, provide boundary-scan control to enable pins, test pins, reset signals, power shutdown circuitry. These signals can be used to disable device outputs that will otherwise conflict with nets involved in boundary-scan test. Examples of methods to disable these devices include:
Connecting a boundary-scan controllable output on the net to control the chip enable of the conflicting device.
Installing a dedicated jumper which put the target into a boundary-scan ready state.
Connecting a GPIO pin available on Corelis JTAG controllers to the offending device.
Considerations for memory cluster testing
All memory control, address, and data pins must be connected to boundary-scan pins. Memory cluster tests are performed by controlling the pins on the memory device using surrounding JTAG logic.
The driving boundary-scan devices must have separate control cells for the address, data, and control pins on the memory device. Some CPU devices have shared control cells, so check the BSDL file to verify each pin has its own control cell.
JTAG needs to control the memory clock, so ensure the clock pin has a JTAG output cell to drive the clock. Additionally, if a PLL is used to drive the clock, ensure that the PLL has a bypass feature that can be used during JTAG testing. Ideally the PLL bypass feature should be controllable using JTAG and some PLLs enable bypass by grounding the AVDD pin. Unfortunately, it needs to be noted that adding stubs or additional circuitry to the clock net may alter the functional operation of the circuit.
If control of the memory clock is not available, consider utilizing ScanExpress JET to test the memory at-speed if it is connected to a supported CPU.
Consider Power Supply Loading
The Update-DR state on all components can induce large current swings and ground bounce, meaning JTAG test power requirements may differ from functional power requirements.
Ensure the power supply and voltage regulators can handle JTAG test current.
Increase the current limit on the power supply. Functional current and boundary-scan test current requirements may widely differ.
The BYPASS instruction can be used to remove components from the test and limit switching.
Identify zero-ohm and low impedance pull-up and pull-down resistors, especially digitally controlled impedance (DCI) nets. During test development these resistors should be treated as transparent components.
Xilinx and Altera FPGA Considerations
Xilinx and Altera FPGA devices have different test characteristics depending on if the devices are configured; maximum testability on these devices is in the pre-configuration state.
To keep Xilinx parts in pre-configuration mode, the INIT* pin needs to be held low prior to and during power-up of the target.
To keep Altera parts in pre-configuration mode, the NCONFIG* pin needs to be held low prior to and during power-up of the target.
We recommend that these pins route to the TAP header in place of a ground pin. When the JTAG controller plugs into the TAP, the pin will automatically be pulled low.
Compliance Enable Pins Must Be Satisfied
Compliance pin states are listed in the BSDL file and correct compliance pin states must be maintained prior to and during JTAG testing to maintain test compliance.
For example, the BSDL file for the Motorola MPC106 device describes the following compliance enable pin:attribute COMPLIANCE_PATTERNS of mpc106: entity is “(LSSD_MODE_L) (1)”;indicates that pin LSSD_MODE_L must be a logic high prior to and during boundary-scan testing for correct JTAG operation.
Considerations for Flash In-System Programming
In-system programming of flash devices through JTAG is done by emulating read & write cycles to the flash device using surrounding JTAG logic including address pins, data pins, chip enable, output enable, write enable, and optionally reset, write protect and ready/busy.
The driving boundary-scan devices must have separate control cells for the address, data, and control pins on the memory device.
To reduce programming time:
Ensure that your scan-chain is short.
Remove unnecessary constraints.
Use external write strobe.
External Write Strobe
The WRITE_STROBE* signal is active low and should be pulled high with a 1K resistor on the target board. It should be logically OR-ed with the WRITE_ENABLE* signal so that assertion of either the WRITE_ENABLE* signal or the WRITE_STROBE* signal will assert the flash WE* pin
Flash In-System Programming Theoretical Speed Formula
(#bits in chain) * (#scans/write) * (#writes/location) * (#locations) TCK frequency
Where: #bits in chain – effective length of the boundary-scan chain (assuming unused components are placed in BYPASS) #scans/write – number of DR scans which are required in order to write a data value to the flash #writes/location – number of data values that must be written to program each location #locations – number of data locations to be programmed TCK frequency – frequency of the JTAG test clock (TCK) signal
PCB Layout Considerations
Design-for-testability needs to be considered during layout to prevent signal integrity problems and ensure a working scan chain.
TCK needs to be as free as possible of glitches and spikes, since all operations are triggered by rising and falling TCK edges.
Connection of TDO of last device in scan chain to board TDO should be as short as possible.
TCK and TMS fan out to every device is most critical. When using fan out buffers to distribute TCK, TMS and TRST_N, put termination resistors on the primary side of the buffer (signals coming
from the JTAG controller).
A series resistor on the TDO of the last device in the chain should be close to that device’s TDO pin.
Provide adequate room around the TAP connector to accommodate mating cables. For example, consider cable access when the product is enclosed or fully assembled.
Debug access is easiest when termination resistors are placed consistently close to the TAP connector along with a clearly labeled ground point.
Do not place the TAP connector near noisy analog components such as voltage regulators.
Consider access to probe the scan-chain if things don’t work; it may be necessary to attach physical instruments to the scan chain pins.
Place JTAG devices such that a star topology can be implemented on the JTAG signals.
Recommend general documented layout guidelines include:
A Practical Guide to High-Speed PCB Layout, Analog Devices
Guidelines for Designing High-Speed FPGA PCBs, Altera
High-Speed Board Layout Guidelines, Altera
Basic Principals of Signal Integrity, Altera
Recommend JTAG traces be a minimum 10 mil width with minimum 10 mil spacing with length as short as possible JTAG signals should be routed on the outer layers away from noisy analog voltage regulators 36
TMS and TCK are broadcast lines. They should be routed in accordance to high-frequency bus rules. Use fan out buffers to avoid overload of TMS and TCK signals coming from the JTAG controller.
Route TCK and TMS in a star topology
Signal quality is a key factor for successful JTAG testing
JTAG test signals should be assigned as critical for first pass route
Faster TCK results in faster in-system programming times
Compliance enable pins should be accessible. It is a good idea to place pads for both pull-up and pull-down resistors on the pin when in doubt
Even though TDI and TDO are point to point, consider an accessible test point at each link for debug if required
Always ensure there are convenient test point locations for ground
Debug is much easier with the ability to clip one lead to ground
A working scan-chain should be one of the highest priorities
Breaking up a scan-chain may provide easier debug capability
Different groups use the JTAG chain differently
Designers need JTAG for in-circuit emulation and in-system programming
Test engineers need JTAG for interconnect testing
Design engineers will benefit by implementing a boundary-scan friendly design. Learn More. For more tips on boundary-scan chains, see boundary-scan chain tips.
Corelis is the leader in providing embedded hardware test solutions, called ScanExpress, the industry’s broadest line of JTAG Boundary-Scan software and hardware products that combine exceptional ease of use with advanced technical innovation and unmatched engineering support.
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