Boundary-Scan Chain Design for Testability
Successful testing and ISP of your design depends on a fully functional boundary-scan chain. Maximum test coverage is achieved by testing all JTAG devices simultaneously.
Place all JTAG devices into a single scan-chain and add test points for debug access—all JTAG devices are tested simultaneously in the serial chain.
Multiple scan-chains are acceptable but should be merged externally; in some cases this is the preferred method:
- Use a multi-TAP JTAG controller to externally combine multiple JTAG scan-chains into a single chain. Each JTAG TAP is actively buffered and can interface to different voltage levels.
- Alternatively combine multiple chains with a fixture or cable. Lower reliability and susceptible to noise.
Scan Chain Debug Access & Test Points
Resistors can be designed into the scan chain as a way to selectively bypass devices in the scan chain for debugging.
Check devices for full JTAG compliance
Not all devices fully comply to the IEEE-1149.1 standard. When analyzing or troubleshooting devices, consider the following cases and guidelines.
- Some devices support emulation only or ISP only and cannot be utilized for interconnect tests. Check datasheets, device errata and BSDL files.
- Place devices that do not include a boundary-scan register or do not support the EXTEST instruction in BYPASS.
- Group components with similar voltage levels and utilize a multi-JTAG TAP controller for programmable voltage interfacing or add level shifting components to the design.
- Treat TCK as a critical high speed clock signal during layout.
- Always consider signal loading on the common signals TCK and TMS and proper routing for good signal quality. When driving a large number of JTAG devices (more than 5), add TCK and TMS buffering.
- Dedicate a schematic page for a block diagram of the JTAG scan-chain.
JTAG Interface Connector (TAP)
Corelis recommends the Corelis JTAG TAP pin-out for robust one-to-one connection between the JTAG controller and the target.
Additional guidelines include:
- A solid ground is very important; every other pin on Corelis TAPs is ground on cable providing noise immunity.
- Follow the IC vendor’s JTAG signal termination guidelines first, then Corelis’ guidelines.
- When using Multiple JTAG TAP connectors:
- Group components by IC vendor.
- Group components by voltage.
- Group components by maximum device speed.
- Group by devices that require the TRST_N signal.
- Use jumpers or additional logic to isolate devices for debugging.
The IEEE-1149.1 standard does not define type of connector used for JTAG, so there is a wide variety of options when selecting a connection method.
- Although the pinouts may be different, most vendors use standard 0.1″ x 0.1″ pitch headers.
- Shrouded header recommended to prevent incorrect insertion.
- Additional connector types include:
- 2mm connectors.
- 0.050″ x 0.050″ pin spacing.
- Test points for fixture probe access to JTAG signals.
- Edge connectors.
- A backplane.
- Keep JTAG TAP cables as short as possible. Cables should ideally be under 12″ in length, but shorter is better!
- When using custom cable adapters, ensure adequate grounding is provided between the JTAG controller and the target.
- Third party JTAG tools may require a separate JTAG TAP connection for an individual component.