Improve Flash Programming Speed with Firecron JTS15S

Home Education Design for Testability Tips and Guidelines Improve Flash Programming Speed with Firecron JTS15S

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Improve Flash Programming Speed with Firecron JTS15S

Flash memory sizes have continuously grown to accommodate more product features, but more data leads to longer flash programming times and increased production overhead. Programming throughput has become a critical factor to improve production rates and remain competitive.

1 1 - Improve Flash Programming Speed with Firecron JTS15S

The JTS15S core provides an IEEE-1149.1 compatible interface with minimal overhead to improve programming speeds.

Firecron’s JTS15S core is a unique method of reducing flash programming time over the IEEE-1149.1 interface—by minimizing the size of the boundary-scan register, in-system-programming (ISP) speeds can be greatly increased to reduce manufacturing time. Fully compatible with Corelis’ ScanExpress suite of boundary-scan software, JTS15S is the ideal way to boost ISP performance. .

Features & Benefits

  • Improve flash programming and verify times by up to 90%.
  • Place signal safe states to ensure no loss of boundary-scan register control during flash programming.
  • Maximize the TAP clock frequency for further reduction in flash programming times.
  • Leverage an existing system FPGA or CPLD, or use a Firecron Gateway device to partition scan chains and implement the JTS15S device on a board to streamline in-system-programming

Applications

  • Manufacturing—Rapidly program flash in-system with the same software and hardware used for IEEE-1149.1 boundary-scan test.
  • Field Updates—Utilize the ubiquitous JTAG port for fast flash programming to upgrade systems in the field.

Additional Resources

Firecron JTS15S Support Data Sheet
AN 16-0519: Using Firecron JTS15 IP with Corelis ScanExpress Software