The IEEE-1149.1 standard, also known as JTAG or boundary-scan, has for many years provided an access method for testing printed circuit board assemblies, in-system-programming, and more. But what is JTAG, and how can it be used to benefit organizations in diverse industries across all phases of the product life cycle?
What is JTAG?
JTAG is an integrated method for testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level. JTAG is commonly referred to as boundary-scan and defined by the Institute of Electrical and Electronic Engineers (IEEE) 1149.1, which originally began as an integrated method for testing interconnects on printed circuit boards (PCBs) implemented at the integrated circuit (IC) level. Since JTAG’s introduction as an industry standard in 1990, JTAG has continuously grown in adoption, popularity, and usefulness—even today, new revisions and supplements to the IEEE Std.-1149.1 standard are being developed and implemented. This document is a brief introduction to the nature and history of JTAG, from its introduction to new extensions in current development.
JTAG Test Overview
While originally developed to address the needs of testing printed circuit board assembly (PCBA) interconnects, JTAG test methods can be used to address many needs beyond simple structural test. This overview will briefly examine popular types of JTAG tests and applications.
Technical Guide to JTAG
This technical primer provides a brief overview of JTAG devices–basic chip architecture, essential capabilities, and common system configurations. The basic properties of the boundary-scan description language (BSDL) are also covered.
JTAG Test Applications
New developments and applications of the IEEE-1149.1 standard have enabled the use of JTAG in many other product life cycle phases. This tutorial describes how JTAG technology is now applied to product design, prototype debugging, and even field service, allowing the cost of JTAG tools to be amortized over the entire product life cycle.
Design for Testability (DFT) Guidelines
The earlier a mistake or a defect can be detected in the design phase or in the production process, the less money it will cost to remedy it and the sooner the product will be ready for production or shipment. Therefore, a good Design-For-Test (DFT) strategy is needed for the design, prototype and production phase of a product.
JTAG is a widely practiced test methodology that is reducing costs, speeding development, and improving product quality for electronics manufacturers around the world. By relying on an industry standard, IEEE 1149.1, it is relatively quick, easy, and inexpensive to deploy a highly effective test procedure. Indeed, for many of today’s PCBs, there is little alternative because of limited access to board-level circuitry. This paper highlights just some of the potential applications of the JTAG standard in various stages of the product life cycle, each contributing to the overall effect of significantly reduced product development and support costs.
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