JTAG Boundary-scan Test Coverage Q and A

Introduction
Our applications engineers recently had an interesting discussion with a client about interpreting test coverage report data. It’s not always clear what test coverage is available to a net, nor is it easy to determine the full extent of test coverage that can be achieved when dealing with non-boundary-scan components. What does partial coverage really mean? If a net has complete coverage, is it impossible for a defect to escape?
In this series, we’ll take a look at the coverage provided on resistors, capacitors, and Flash memory control signals.

JTAG Boundary-scan Test Coverage Q and A
Part 1: Resistors
Q: Some Pull-Up resistors are marked with PARTIAL test coverage and not COMPLETE. Why?
A:
First, let’s discuss the implications of being classified as a Pull-Up resistor in ScanExpress TPG. If the resistor is identified in the report as a Pull-Up (PU) or as a Pull-Down (PD), then that simply means that one pin of this resistor connects to a power or a ground net (as specified in the Power/GND step). Simply being marked as a PU or a PD resistor does not mean that there is a PU or PD resistor test for this device.
In order for tests to be created, there also must be a boundary-scan controllable cell available to drive on the other pin of the resistor and being able to sense is back (a bidirectional cell or an output3 paired with an input cell, as shown in Figure 1).

 PARTIAL

Figure 1. Diagram of a 3 step pull-up resistor test using an output3 cell paired with an input cell.
Note: This diagram uses the convention of ‘1’ and ‘0’ for ‘high’ and ‘low’ values for output from the pin and ‘H’ and ‘L’ for values ‘high’ and ‘low’ values input to the pin. This same convention is used in Corelis ScanExpress Tools.

If the boundary-scan cell is not capable of driving the signal, then the resistor will be classified with partial coverage. Thus, the non-power or ground side of the resistor gains no test coverage, while the power or ground side gains partial coverage due to short detection on the power or ground net as long as there is a sense-capable boundary-scan pin on that power or ground net.

Q: Ok, but I have rightfully identified that the above requirements are met. Why is the resistor still not identified with COMPLETE coverage?
A:
There are likely restrictions during test generation preventing the test vectors from creating a complete test. Constraints imposed on the vector generation engine—in particular those constraints that force a net to be driven or sensed at a specific value—will limit the TPG engine’s ability to create complete tests. Also consider constraints that are used to disable components; these constraints will also cause the vectors to fix certain signals used to disable the Flash or RAM device.

For example, in Figure 2 below a boundary-scan component connects to two pull-up resistors, R1 and R2. The R1 resistor is also connected to Flash chip enable pin CE1n.

Example Flash Chip

Figure 2. Example Flash Chip Enable Connection diagram.

The TPG preparation software will generate a constraint to disable the Flash that fixes the CE1n net ‘high’ in all but the Flash test step. This same constraint means that the tool will not attempt to drive CE1n to any value other than ‘high’ during other test steps in order to keep the Flash disabled. Thus, R1 will not be tested in the pull-up/pull-down test and will not have complete coverage.

In the case of R2, which is not part of the Flash disable command, the TPG generation engine has no problem driving the net ‘low’ during the resistor test; thus, the resistor 2 test coverage is identified as COMPLETE since both short and open faults can be detected. The same concept applies to the other PU signals on control pins that are essential to disabling the Flash component, such as ‘write enable.’

Q: Is it possible to get coverage on ALL PU resistors?
A:
Yes, it is! However, the user must intelligently determine if it is safe to allow the test generation engine to toggle the control pins all at the same time for the patterns. For example, it may be unsafe to drive some of the Flash control signals low during interconnect and pull-up/pull-down testing.

In order to get the additional test coverage, one could simply remove the constraint for the resistor step only. For example, it is not uncommon to remove certain DISABLE lines from the constraints for a particular test step. This can be done either using custom constraint file or by utilizing local constraints for certain test steps.

Conclusion
Resistor test coverage depends on the environment—lack of boundary-scan access or conflicting constraints will limit the ability of the ATPG tool to create test vectors that exercise the resistor nets. Do you have a questions about test coverage you would like to see addressed? Let us know!

Published On: November 29, 2012Categories: Corelis Boundary-Scan Blog, JTAG Boundary-Scan

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