ScanExpress DFT Analyzer
Test coverage statistics provide engineers and managers valuable information to make critical decisions in product development and manufacturing.
ScanExpress DFT Analyzer is an automatic test coverage analysis tool for printed circuit boards and systems that include a mix of boundary-scan and non-boundary-scan devices. The tool assists design and test engineers to increase fault coverage and reduce boundary-scan test procedure development times. Using ScanExpress DFT Analyzer results in better informed test decisions.
Ideally ScanExpress DFT Analyzer is used after schematic capture and before PCB CAD layout. At this stage of product development, the tool creates a comprehensive set of test coverage reports that identifies all nets, pins, and devices, classifying them as completely tested, partially tested, and not-tested
Features
- Generates both detailed and summary test reports at the device, net, and pin level for tests generated by Corelis ScanExpress TPG™
- Identifies incorrect compliance enable pin states, IEEE-1149.6-compatible pins, and more
- Integrated Report Browser interface
- Customizable analysis: include or exclude specific nets, buses, pins and devices
- Exports test coverage data to a spreadsheet or database for integration with other test equipment reports
- Produces Fabmaster-compatible reports that help eliminate test pads for fixture based testers resulting in reduced test fixture cost, size, complexity, and production schedule
Applications
Design Engineers
Design Engineers are able to establish and validate board test coverage before committing to layout.
Test Engineers
Test Engineers are better informed to create more complete test procedures.
Design and Test Engineers
Design and Test Engineers can increase fault coverage and reduce boundary-scan test program development time by identifying fault coverage limitations.
Benefits
- Establish exact boundary-scan test coverage
- Prepare test coverage reports for management
- Reduce the number of PCB test points
- Find test holes and deficiencies
- Increase fault coverage
- Reduce test procedure development time