Features

• Dramatically enhances UUT test coverage when it includes a CPU with a JTAG debug/emulation port
• CPU assists at-speed testing using test routines downloaded via JTAG into CPU cache memory or external RAM
• JTAG Embedded Tests are able to be combined with boundary-scan structural tests for extended test coverage
• Automatic generation of functional tests for common peripherals
• Software guides the user through a logical sequence of steps for constructing test steps from start to finish
• “C”-style command file script language with single-step capability assists in writing custom test sequences
• Extends coverage beyond boundary-scan for:
  • All CPU accessible resources
  • Boundary-scan inaccessible components and analog devices
  • I/O port testing using external equipment
• In-System Programming (ISP) of Flash up to theoretical speeds
• Large library of supported processors
• Automatically constructs test plans for integration into the ScanExpress Runner™ test execution sequencer (sold separately)

JET automates at-speed functional test development of peripheral components that interface with an IEEE-1149.1 compatible CPU. JET provides a peripheral component library that allows reusability across multiple CPU platforms. The highly customizable diagnostic scripts provide users with the pinpoint resolution they need to clearly identify failures. Corelis offers both a stand-alone JET solution as well as a combined solution with traditional JTAG structural interconnect testing. JET is ideal for testing boards without the need to modify the PCB circuitry or the on-board firmware.  JET operates through a CPU’s

Combining JTAG and Functional Test to Increase Test Coverage

JTAG port to provide users simplified access to the following operations:

• Run, Stop, and Step Functions
• Ability to Write to Registers and Memory
• Ability to Read from Registers and Memory
• Exchange Parameters with the JTAG Host
• Display CPU Status

The host software automatically uses these features to download test & diagnostic routines into the CPU’s cache or external memory. These routines then execute at full processor speed and send results back to the host.

JET Supported Processors

Altera Cyclone V SoC	NVIDIA TEGRA K1
NXP i.MX35 NXP i.MX51 NXP i.MX6 NXP MPC56xx NXP QorIQ P1 NXP QorIQ P2 NXP QorIQ T2	Texas Instruments AM DM37xx Texas Instruments AM 18x Texas Instruments 335x
	Xilinx Zynq-7000

Methodology

Corelis pioneered JTAG emulation and has provided customers with thousands of JTAG emulators for many CPU types. Corelis is also the world leader in boundary-scan test tools. Combining these two technologies into one product provides customers with an integrated development and execution test environment with a single point of contact and support.

The JET testing method depends on the UUT having a JTAG-enabled processor (CPU) on-board. The CPU dedicated JTAG Test Access Port (TAP) is generally routed to a single emulation connector on the board. Other JTAG interconnect scan chains may be connected to different JTAG connectors which are used for boundary-scan testing.

The CPU debug TAP brings control and visibility of the processor itself to the host. This is the same TAP employed by JTAG emulators for software development and debug. Included are access to the CPU register/control structures, attached memory, and the ability to utilize the CPU debug running/stepping facilities for testing.

The JET method harnesses the power of the target embedded CPU to assist in the code download, device programming, and testing operations at full processing speed. Several basic features are available:

• Run

• Stop

• Step

• Write to Registers and memory

• Read from Registers and memory

• Exchange parameters with the JTAG host

• Display CPU status

The host software uses these features to download test/diagnostics routines into the CPU’s cache memory and into the target memory. These routines execute at speed and pass the test results to the host.

There is no need to modify the on-board application software, typically stored in Flash memory. The Flash memory itself can be similarly programmed using the CPU as an algorithm expediter. This avoids the slower wiggling approach of JTAG Flash programming.

Connecting to a UUT

JET requires a UUT with a JTAG-enabled processor having external access to its Test Access Port (TAP). A Corelis controller serves as the interface between the PC and the TAP interface.

Boards typically include a single JTAG TAP connector that is dedicated to the CPU. This TAP is often used for JTAG–based software debug and emulation. Boards may also include other JTAG TAP connectors, primarily being used for boundary-scan test and in-system programming.

The figure above depicts connecting a Corelis NetUSB-1149.1/E™ four-port JTAG controller to a board that includes three separate TAP connectors: a CPU with a dedicated JTAG port, and two additional JTAG ports containing other boundary-scan compatible devices.

The ScanExpress JET system is also able to handle cases where the CPU and other boundary-scan devices share the same scan-chain.

Using ScanExpress JET

The ScanExpress JET tool is available as a stand-alone application or as a plug-in to ScanExpress TPG. Functional tests that are generated using ScanExpress JET are also compatible with the ScanExpress Runner test executive. Figure 2 depicts the ScanExpress JET GUI.

Figure 2. ScanExpress JET GUI

The ScanExpress JET Integrated Development Environment (IDE) consists of the following major functions:

1. Preparation – Several screens that guide the user step by step on how to collect information about the devices and setup of various test options. Following these steps, the tool automatically produces the functional test steps.

2. Test Steps – Program that executes the test steps that were previously created by the preparation function.

3. Reports – Analysis program to view and calculate test coverage statistics.

4. Execution with the ScanExpress Runner option – Invokes the ScanExpress Runner test executive to run both boundary-scan and JET tests from a single test plan.

ScanExpress JET has the ability to record all feature selections and file references to enable recalling a given project. This serves as a mechanism to quickly retest previous target boards as well as providing a starting point for migrating similar test scenarios.

When operating as a plug-in to ScanExpress TPG™, ScanExpress JET inherits the boundary-scan environment parameters, including all settings and files of the host application.

Preparation

This constitutes a set of sequential screens which guide a user in selecting options and declaring device specific parameters. It collects all the information required to perform automatic testing using the JET methodology. It also includes optional JTAG operations to assure minimal board connectivity at the outset.

The major pieces of information required by the tool include::

1. Devices – The tool requires knowledge of CPU visible resources in the circuit. This includes information such as memory device features including size, width of the addresses, etc. Much of this information can be obtained automatically by the tool.

2. Custom test scripts – User developed test routines beyond those automatically created by the tool.

The information collected becomes part of the project when saved.

Completion of the Preparation phase results in the automatic creation of scripts, download routines, and embedded testing steps required to perform specific board testing.

Test Steps

The Test Steps screen lists the test steps automatically created during the preparation phase and provides controls to run tests on the target and view results. The steps can be invoked individually, run in their entirety or with an enabled subset, and can even be looped.

Progress while the steps are underway is also indicated.

This screen shows a PASS/FAIL indication summarizing the overall outcome of all enabled test operations. Detailed diagnostics of failure causes is displayed.

Reports

The Reports function provides access to test coverage statistics enabling the user to determine the overall testability utilizing ScanExpress JET. Included are merged coverage statistics showing how well testing confirms board operability. Coverage information includes both JET steps as well as legacy boundary-scan tests.

ScanExpress Runner

ScanExpress JET test steps can be executed from the ScanExpress Runner environment. ScanExpress JET will automatically pass the generated test files to ScanExpress Runner. Clicking on the Runner icon in the shortcut pane on the left side of the ScanExpress JET main window launches ScanExpress Runner.

Using ScanExpress Runner to execute boundary-scan tests in conjunction with JET based tests provides a single test environment for a complete test using both test methods. Verifying structural integrity with JTAG interconnection test prior to running JET functional tests results in better overall diagnostics during failure conditions.