Corelis ScanExpress JET represents a major step forward for automatic circuit board testing. The JTAG Embedded Test (JET) method extends coverage beyond popular boundary-scan techniques to virtually every signal of the UUT that is accessible by on-board CPU(s). This includes most of the remaining non-scannable, analog and I/O port resources.

Here is a list of some important JET Benefits:

1. JET augments UUT structural test coverage with functional tests when UUT includes CPU device(s) with JTAG debug/emulation port(s).

2. JET automatically generates functional at-speed tests for memories and flash devices, saving months of coding, tedious UUT tests debugging and significantly reducing the overall tests development costs. Intuitive GUI guides the user through a logical sequence of test preparation steps, followed by automatic generation of functional test steps from start to finish.

3. JET functionally tests components at-speed using embedded tests that are downloaded via JTAG into CPU cache memory or RAM. This increases test reliability and helps you diagnose failures, especially when the board does not boot.

4. JET uses the same Boundary-scan test station setup and GUI as ScanExpress Runnerfor structural and functional testing and in-system programming. Using a single JTAG controller for boundary-scan, functional (emulation) tests and programming greatly reduces costs and test fixture complexity.

5. JET can help overcome poor design-for-test (DFT) in the circuit board to some degree when boundary-scan test and JTAG embedded test are coupled in a unified test methodology.

6. JET is able to run tests continuously and rigorously to detect hard to find power and ground structural defects. Special memory tests exercise UUT functionally to make sure that Power and ground pins are properly connected. Typically power and ground pins constitute 10-20% of high density device pin count and there is no easy way to test that these pins are all connected. Further, there is no way to detect open ground or power pins as often a device will work OK even if several of its power and ground pins are not connected. Often such a device, with some open ground and/or power pins, may pass boundary-scan tests and even power-up tests and this manufacturing defect may go unnoticed until intermittent behavior is observed in the field.

7. JET provides highest speed Flash and serial EEPROM in-system programming. Devices can be programmed at or close to the theoretical programming speed and save time in development and production phases.

8. JET is a great tool for testing, diagnosing and troubleshooting ‘bone pile’ of functionally inoperable UUTs that pass boundary-scan tests but fail functionally.

9. JET extends at-speed coverage beyond boundary-scan for:

   • All CPU accessible resources such as memories, CPLDs, FPGA, UARTS, etc.

   • Non-scannable and analog devices

   • Memories with clock that cannot be controlled by boundary-scan

   • I/O testing using external equipment

   • JET Memory tests are run at speed and therefore can test the entire memory – a feature that cannot be provided by BS.

10. JET reduces or eliminates the use of In-Circuit Testers (ICTs) and Flying probes saving you time and cost.

11. JET automatically constructs test plans that can be executed directly via ScanExpress Runner™ simplifying test plans generation and reducing mistakes.

12. JET’s “C”-style script language with a single-step capability assists in writing custom tests and farther increasing the test coverage and diagnostics. It also accepts pre-compiled user embedded tests/code so that users can re-use existing diagnostics code.

13. JET has a continuously growing list of supported processors and peripherals.