IEEE-1149.6 Support

IEEE-1149.6 Support

For ScanExpress™ Tools


The proliferation of high speed serial interfaces in modern printed circuit board designs created a challenge that existing test methodologies could not address. The IEEE-1149.6 standard was developed to address that challenge by modifying the existing boundary-scan architecture and introducing test coverage on AC-coupled differential interconnections between ICs (integrated circuits). Utilizing the existing JTAG interface, IEEE-1149.6 provides the least intrusive methodology to test these advanced digital networks.

ScanExpress™ Tools

The ScanExpress automatic test development suite provides full support for the IEEE-1149.6 standard by scanning a PCB netlist to detect, model, and classify devices involved in AC-coupled circuit topologies. IEEE-1149.6 tests are generated automatically and transparently for the user, providing a seamless solution.

What is IEEE-1149.6?

Ratified in 2003, IEEE-1149.6 provides support for boundary-scan testing of high speed AC-coupled interconnects.

AC Coupled Nets

IEEE-1149.1 was designed for DC interconnects and does not address high speed AC coupled signals. 1149.6 expands on 1149.1 by providing a standard method for testing across AC coupled nets.

Differential Nets

IEEE-1149.6 introduces new features to expand test coverage and address complex circuit topologies associated with high speed differential signals.

Test Development Automation with ScanExpress

Using a combination of auto-detection, filtering, and parametric search, ScanExpress tools can identify key elements of IEEE-1149.1 and IEEE-1149.6 circuit topologies, including:

  • 1149.1 & 1149.6 Components
  • Series, Pull-up, Pull-down, & Termination Resistors
  • Power, Ground, & Intermediate Voltages
  • Series Capacitors


  • An intuitive wizard guides the user through the construction of complete test procedures
  • Automatically generates test patterns for infrastructure, interconnect, memories, FIFOs, clusters, and resistors using proven, mature boundary-scan test algorithms
  • Test management functions for creating project revisions and test variations within a single parent test project
  • Detects and supports industry standard CAD netlist formats
  • Identifies the boundary-scan chain order and draws a graphical representation of the boundary-scan chain
  • Finds and classifies all resistors and resistor packs as either pull-up, pull-down, series, differential termination, or non-testable resistor types
  • Complex script language with integrated debugging environment assists in writing custom boundary-scan test steps
  • Constructs test plans for integration into the ScanExpress Runner™ test execution sequencer (sold separately)
  • Assembles detailed fault coverage analysis reports for use with the ScanExpress DFT Analyzer™ (sold separately)
  • Single Integrated Development Environment (IDE) for all JTAG applications simplifying test development, execution, and analysis
  • Complies with IEEE standards 1149.1 and 1149.6
  • Compatible with Microsoft Windows 7, Windows 8/8.1 and Windows 10

The ScanExpress TPG Interface

TPG leverages a versatile IDE to provide automation and guidance for all users without sacrificing customizability and power. Development consists of two distinct phases: Preparation and Generation. By guiding the user through the process of defining the UUT, TPG creates a comprehensive boundary-scan test in a matter of minutes.

ScanExpress TPG - IEEE-1149.6 Support
The ScanExpress Preparation Windows with Topology Viewer

The Preparation Phase

ScanExpress TPG test development begins by gathering details about the UUT from the user in an interactive session through a series of steps. The intelligent preparation engine assists the user with assigning input files, identifying special nets, and modeling devices on the UUT.

TPG features a comprehensive and ever-expanding library of device models for popular devices including resistors, buffers, RAM, Flash, and many more. The automatic association features quickly find models every step of the way.

ScanExpress TPG optionally logs all part numbers and associated data within each project for re-use in additional projects, further reducing new test development time.

The Generation Phase

The Generation phase provides tools to further personalize, fine tune, and generate test files. The user is free to directly modify the
The ScanExpress TPG Generation Window
input files, add customized test steps, and utilize TPG’s advanced “C”-style boundary-scan scripting language with integrated debugging environment to edit or create adaptive and interactive test steps.
When the user is ready to compile tests, the state-of-the-art automatic test pattern generation (ATPG) engine creates test steps ready-to-run in the ScanExpress Runner™ test execution sequencer.

ScanExpress TPG Generation - IEEE-1149.6 Support
The ScanExpress TPG Generation Window
1149 6 Support - IEEE-1149.6 Support
ScanExpressFlow icon - IEEE-1149.6 Support

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