Functional circuit board testing presents many challenges that are often costly and time-consuming. Most functional tests need to be customized for each design, limiting reusability. This results in software engineers vying for the time between development code and test code. Even when functional tests become available, the diagnostic details are often inadequate to give clear visibility on a given problem. Join us April 20, 2021, @9:00 a.m. PST for a deep technical dive into ScanExpress JTAG Embedded Test (JET) One-hour Session Engineering Training.
JTAG Boundary-Scan Training Classes for 2021
Corelis offers free three-day training classes that include a boundary-scan tutorial and hands-on lab exercises using Corelis ScanExpress hardware and software. The training class covers all aspects of boundary-scan testing using Corelis ScanExpress tools. Design for testability (DFT), JTAG embedded functional test (JET), in-system programming (ISP) and test procedure generation are also covered.
The training includes a combination of lectures, demonstrations, and hands-on exercises using actual hardware to provide you with an overview of ScanExpress test and ISP features and to have you run your own developed test.
January 19-21, 2021 March 16-18, 2021
May 11-13, 2021
July 20-22, 2021
September 14-16, 2021
November 9-11, 2021
Training Class FAQ
Who should attend?
This class is intended for design engineers, test engineers, and managers who plan to use boundary-scan test methodology and the Corelis ScanExpress family of products. Previous knowledge of boundary-scan technology is not required.
How can I prepare for the class?
What will I learn?
Upon completion of the training you will be able to correctly implement boundary-scan DFT and ISP facilities into your new designs. You will also be able to develop boundary-scan test procedures on your own as well as in-system programming files for CPLDs and Flash memories.
Topics covered in the class include:
- Introduction to boundary-scan
- Design for boundary-scan testability Guidelines
- Design for boundary-scan In-System Programming Strategy
- Test generation and testing methods for boundary-scan-based designs
- Test program generation methodology
- Test program execution plan
- Test program interactive debugging concepts
- At-speed embedded functional testing using an on-board JTAG-based CPU
- In-system programming of CPLDs and Flash memories tutorial
- Hands-on individual lab exercises using real Units Under Test (UUTs) that will teach you:
- How to generate and execute interconnect tests
- How to test memory interconnects
- How to test logic clusters
- How to use an embedded processor’s JTAG port for embedded functional testing
- How to program CPLDs and Flash memories in circuit
- How to troubleshoot a test procedure
You will become familiar with the entire Corelis ScanExpress product family, including:
- ScanExpress TPG
- ScanExpress JET
- ScanExpress DFT Analyzer
- ScanExpress Merge
- ScanExpress Runner
- ScanExpress ADO
- ScanExpress Viewer
- ScanExpress Debugger
- ScanExpress Programmer
- ScanExpress Flash Generator
How can I get more information and register?
For additional schedule and registration information about training classes, please contact:
+1 (562) 926-6727
Classes are subject to cancellation two weeks prior to start date.
Classes held at the Corelis Headquarters are no-charge.
On-site training classes are available. Contact your Corelis sales engineer or email@example.com for scheduling and pricing information.