Training and Seminars 2023: Embedded Hardware Systems Test with IEEE-1149.x and Beyond
Corelis offers free three-day training classes that include a boundary-scan tutorial and hands-on lab exercises using Corelis ScanExpress hardware and software. The training class covers all aspects of boundary-scan testing using Corelis ScanExpress tools. Design for testability (DFT), JTAG embedded functional test (JET), in-system programming (ISP) and test procedure generation are also covered.
The training includes a combination of lectures, demonstrations, and hands-on exercises using actual hardware to provide you with an overview of ScanExpress test and ISP features and to have you run your own developed test.
LIVE WEBINAR & ONSITE TRAINING CALENDAR
- Nov. 14, 10:00 – 11: 00 AM PST: Design for Testability (DFT): Planning a Successful Approach to Embedded Hardware Test with IEEE-1149.x: Register here
- Registration is Closed: Dec 5, 6, & 7: Onsite Three-day Training – Embedded Hardware Engineer, In-person, Hands-on JTAG Boundary-Scan Training
Register on the form below: Feb 27, 28, 29 2024 Onsite Three-day Training (Location: 13100 Alondra Blvd., Suite 102, Cerritos, CA 90703)
Register for Training
Please provide the requested information to register for a training class at our facility in Cerritos, California.
On-demand Webinar | Training
- Design-For-Testability (DFT) for Circuit Board Designers using the IEEE 1149.x Standards, 1-Hour Webinar, View On-demand
- JTAG Boundary-Scan Engineering Webinar Three-day Training, View On-demand (session 1, session 2, session 3, session 4, session 5)
- Planning a Successful Approach to Embedded Hardware Test with JTAG Boundary-Scan IEEE-1149.x, 1-Hour Webinar, View On-demand
- An Introduction to JTAG Boundary-Scan, Good Circuit Board Design Practices, & Common Applications, View On-demand
Training Class FAQ
Who should attend?
This class is intended for design engineers, test engineers, and managers who plan to use boundary-scan test methodology and the Corelis ScanExpress family of products. Previous knowledge of boundary-scan technology is not required.
How can I prepare for the class?
What will I learn?
Upon completion of the training you will be able to correctly implement boundary-scan DFT and ISP facilities into your new designs. You will also be able to develop boundary-scan test procedures on your own as well as in-system programming files for CPLDs and Flash memories.
Topics covered in the class include:
- Introduction to boundary-scan
- Design for boundary-scan testability Guidelines
- Design for boundary-scan In-System Programming Strategy
- Test generation and testing methods for boundary-scan-based designs
- Test program generation methodology
- Test program execution plan
- Test program interactive debugging concepts
- At-speed embedded functional testing using an on-board JTAG-based CPU
- In-system programming of CPLDs and Flash memories tutorial
- Hands-on individual lab exercises using real Units Under Test (UUTs) that will teach you:
- How to generate and execute interconnect tests
- How to test memory interconnects
- How to test logic clusters
- How to use an embedded processor’s JTAG port for embedded functional testing
- How to program CPLDs and Flash memories in circuit
- How to troubleshoot a test procedure
You will become familiar with the entire Corelis ScanExpress product family, including:
- ScanExpress TPG
- ScanExpress JET
- ScanExpress DFT Analyzer
- ScanExpress Merge
- ScanExpress Runner
- ScanExpress ADO
- ScanExpress Viewer
- ScanExpress Debugger
- ScanExpress Programmer
- ScanExpress Flash Generator
How can I get more information and register?
For additional schedule and registration information about training classes, please contact:
+1 (562) 926-6727
Classes are subject to cancellation two weeks prior to start date.
Classes held at the Corelis Headquarters are no-charge.
On-site training classes are available. Contact your Corelis sales engineer or email@example.com for scheduling and pricing information.