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Corelis Webinar: JTAG DFT Guidelines for Circuit Board Designers

Webinar: JTAG DFT Guidelines for Circuit Board Designers

In today’s fast paced environment with short time-to-market requirements, it has become increasingly important to design products that allow for early fault and failure detection.

The earlier a mistake or a defect can be detected in the design phase or in the production process, the less money it will cost to remedy it and the sooner the product will be ready for production or shipment. A good Design-For-Test (DFT) strategy is needed during the design process to ensure testability of a product.

Webinar Includes:

  • The fundamentals of testing with JTAG.
  • Board design techniques for producing reliable, high-speed JTAG scan-chains.
  • Designing circuits to enable JTAG testing of non-JTAG components with indirect access.
  • Common hurdles to designing for JTAG testability and their solutions.
  • Optimizing PCB layout for successful JTAG testing.
  • What is Boundary-Scan, History, Applications, Applications, Tools, etc.
DFT Test Coverage Summary Report
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